Patents by Inventor Yasunori Iriyama

Yasunori Iriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7589391
    Abstract: A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 15, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroyuki Ohta, Yasunori Iriyama
  • Patent number: 7282770
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side and a bottom edge of the well, a terminal formed on the semiconductor substrate at an outside part of the diffusion region, and a conductive region contacting with the well, the well being in ohmic contact with the terminal via the conductive region and the semiconductor substrate, the conductive region having an impurity concentration level exceeding an impurity concentration level of the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: October 16, 2007
    Assignee: Fujitsu Limited
    Inventors: Takuji Tanaka, Hiroshi Nomura, Yasunori Iriyama
  • Publication number: 20060220139
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type formed in the semiconductor substrate, a transistor formed in the well, a diffusion region of a second conductivity type formed in the semiconductor substrate so as to cover a lateral side and a bottom edge of the well, a terminal formed on the semiconductor substrate at an outside part of the diffusion region, and a conductive region contacting with the well, the well being in ohmic contact with the terminal via the conductive region and the semiconductor substrate, the conductive region having an impurity concentration level exceeding an impurity concentration level of the semiconductor substrate.
    Type: Application
    Filed: July 14, 2005
    Publication date: October 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Takuji Tanaka, Hiroshi Nomura, Yasunori Iriyama
  • Publication number: 20060202301
    Abstract: A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.
    Type: Application
    Filed: May 15, 2006
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki Ohta, Yasunori Iriyama
  • Patent number: 6849511
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: February 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Publication number: 20040188726
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Patent number: 6784472
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: August 31, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Publication number: 20030181014
    Abstract: After a hard mask layer including an amorphous silicon layer is formed above a silicon substrate, etching is performed by using a mask to form a trench defining active regions in the silicon substrate. The amorphous silicon layer is selectively etched to retract side walls of the amorphous silicon layer, the exposed surfaces of the silicon substrate and amorphous silicon layer are oxidized or oxynitridized to form insulating films, and the inside of the trench is filled with a deposited silicon oxide layer. The unnecessary portion of the deposited silicon oxide layer is removed by chemical mechanical polishing. Thereafter, the amorphous silicon layer 30 is selectively etched. At this time, the insulating film formed on the side walls of the amorphous silicon layer is left above edge areas of the active region.
    Type: Application
    Filed: November 14, 2002
    Publication date: September 25, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki Ohta, Yasunori Iriyama
  • Publication number: 20030173641
    Abstract: A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.
    Type: Application
    Filed: October 30, 2002
    Publication date: September 18, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki Ohta, Yasunori Iriyama
  • Publication number: 20030003666
    Abstract: A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 formed between the first gate electrode and the second gate electrode; and an interconnection electrode 44 buried in a concavity 42 formed in the first gate electrode, the second gate electrode and the insulation film and electrically interconnecting the first gate electrode and the second gate electrode. The interconnection electrode is buried in the concavity formed in the first gate electrode, the second gate electrode and the insulation film, and the interconnection electrodes electrically interconnects the first gate electrode and the second gate electrode, whereby the semiconductor device can have high integration and can be reliable.
    Type: Application
    Filed: August 16, 2002
    Publication date: January 2, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yasunori Iriyama, Tetsuo Izawa
  • Patent number: 4944870
    Abstract: An automatic filtration dewatering system includes a cover to which a filtration raw liquid supply pipe and a pressure air supply pipe are connected. A plate having a filter medium support and a filtrate exhaust pipe is selectively closed by a cover with a pneumatic cylinder vertically moving said cover. Filter medium moving rollers are provided on both sides of the cover and plate, and a sheet-like long filter medium is stretched over said rollers for movement a predetermined distance per one step of filtration.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: July 31, 1990
    Assignee: Kabushiki Kaisha Yagishita
    Inventors: Aisaburo Yagishita, Yasunori Iriyama, Jouichiro Osuga
  • Patent number: 4686043
    Abstract: Disclosed herein is a batch type filter system including a cover provided with a supply pipe for supplying raw liquid and air, a plate having a filter medium support on an upper surface thereof and a filtrate exhaust pipe, said cover being vertically separable from said plate, a plurality of filter medium moving rollers provided on both sides of said cover and said plate, and a sheet-like long filter medium stretched over said rollers and adapted to be moved by a predetermined length per one batch of filtration, said filter medium being temporarily fixedly held between the circumferential portion of said cover and the curcumferential portion of said plate. The improvement in the batch type filter system comprises arcuately curved tension bars provided at such positions where a moving direction of the filter medium is changed and on downstream sides of said filter medium moving rollers, so as to apply a larger tensile force to a central portion of said filter medium than to both edge portions thereof.
    Type: Grant
    Filed: March 26, 1986
    Date of Patent: August 11, 1987
    Assignee: Kabushiki Kaisha Yagishita
    Inventors: Koichi Yagishita, Yasunori Iriyama, Mitsumasa Hirose