Abstract: An ion implantation method includes generating CmHy+ ions (m is such an integer as 4?m?6, and y is such an integer as 1?y?2m+2) using an ion generating material expressed by CnHx (n is such an integer as 4?n?6, and x is such an integer as 1?x?2n+2), and implanting the ions into a wafer.

Abstract: An image forming apparatus comprising a detachable container storing a toner, the image forming apparatus comprising: a lever part movable in an attaching and detaching direction of the container, the lever part also contacting the container when the container is being detached, thereby moving the container in a detaching direction; and a stopper part being latched to the container and preventing the container from moving, a latching of the stopper part and the container being unlatched by a movement of the lever part when the container is being detached.

Abstract: An ion implantation method includes generating CmHy+ ions (m is such an integer as 4?m?6, and y is such an integer as 1?y?2m+2) using an ion generating material expressed by CnHx (n is such an integer as 4?n?6, and x is such an integer as 1?x?2n+2), and implanting the ions into a wafer.

Abstract: An image forming apparatus comprising a detachable container storing a toner, the image forming apparatus comprising: a lever part movable in an attaching and detaching direction of the container, the lever part also contacting the container when the container is being detached, thereby moving the container in a detaching direction; and a stopper part being latched to the container and preventing the container from moving, a latching of the stopper part and the container being unlatched by a movement of the lever part when the container is being detached.

Abstract: A charge pump circuit generates a desired output voltage by stepping up an input voltage. An LCD driver IC and an electronic appliance are provided with the charge pump circuit.

Abstract: A charge pump circuit 31a of the present invention includes: a step-up capacitor Cc2 charged and discharged in repeated cycles; a charger (SW2a to SW2c) that makes a first end T2a of the step-up capacitor Cc2 conduct to an input voltage VR application terminal and makes a second end T2b of the step-up capacitor Cc2 conduct to a ground terminal GND; a first discharger (SW3a and SW3b) that makes the first end T2a of the step-up capacitor Cc2 conduct to a positive voltage output terminal T3 and makes T2b conduct to VR; a second discharger (SW4a and SW4b) that makes T2a conduct to GND and makes T2b conduct to a negative voltage output terminal T4; a first output capacitor Co1 connected to T3, and a second output capacitor Co2 connected to T4. Each time charging of the step-up capacitor is completed, outputting of a positive voltage by the first discharger and outputting of a negative voltage by the second discharger are alternated.

Abstract: A comparator is provided, which compares an input voltage and a reference voltage by using a plurality of inverting circuits connected in series. The comparator includes a first inverting circuit, a second inverting circuit, a feedback path, and a capacitor arranged on the feedback path. The first inverting circuit inverts a difference between the input voltage and the reference voltage for output. The second inverting circuit further inverts the output of the first inverting circuit for output. The feedback path feeds back the output of the second inverting circuit to the input side of the first inverting circuit. The capacitor causes hysteresis such that an increasing threshold and a decreasing threshold of the second inverting circuit corresponding to an increase and a decrease of the input voltage have a difference therebetween.

Abstract: A multiple-format video encoder stores values of the sine and cosine functions in a ROM. According to the externally specified video format, an address calculating circuit calculates the addresses at which to access the ROM. In the multiple-format video encoder, a luminance/color-difference signal generating circuit generates color-difference signals B-Y and R-Y from digital RGB signals. A first multiplying circuit multiplies the color-difference signal B-Y by the values of the sine function stored in the ROM at the addresses specified by the address calculating circuit and multiplies the color-difference signal R-Y by the values of the cosine function stored at the same addresses.

Abstract: A semiconductor device has a multiplicity of DAC channels for performing digital-to-analog conversion of video signals. Signal processing means for delaying processing of signals by a predetermined delay time is provided in at least one DAC channel. The signal processing means functions as a phase inversion means to reduce cross talks between the DAC channels. The signal processing means also functions as a delay circuit to reduce voltage fluctuations in the power supply.

Abstract: A comparator is provided, which compares an input voltage and a reference voltage by using a plurality of inverting circuits connected in series. The comparator includes a first inverting circuit, a second inverting circuit, a feedback path, and a capacitor arranged on the feedback path. The first inverting circuit inverts a difference between the input voltage and the reference voltage for output. The second inverting circuit further inverts the output of the first inverting circuit for output. The feedback path feeds back the output of the second inverting circuit to the input side of the first inverting circuit. The capacitor causes hysteresis such that an increasing threshold and a decreasing threshold of the second inverting circuit corresponding to an increase and a decrease of the input voltage have a difference therebetween.

Abstract: A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over the respective PLL circuit stages to attain the predetermined ratio, with the first PLL circuit stage receiving the first clock and the last PLL circuit stage outputting the second clock. The frequency division ratios distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.

Abstract: A semiconductor device equipped with a DAC channel has a test pattern generation means for storing and generating test patters, and a test clock input terminal. The test pattern generation means generates a test digital signal representing a test pattern based on the high-frequency (e.g. 135 MHz) test clock input to the test clock input terminal. The test digital signal is supplied to the input end of the DAC channel. Using the test digital signals supplied from the test signal generation means, the semiconductor device can be tested in various high-frequency test modes without any tester outputting high-frequency test signals.

Abstract: A semiconductor device equipped with a DAC channel has a test pattern generation means for storing and generating test patters, and a test clock input terminal. The test pattern generation means generates a test digital signal representing a test pattern based on the high-frequency (e.g. 135 MHz) test clock input to the test clock input terminal. The test digital signal is supplied to the input end of the DAC channel. Using the test digital signals supplied from the test signal generation means, the semiconductor device can be tested in various high-frequency test modes without any tester outputting high-frequency test signals.

Abstract: A semiconductor integrated circuit device has an output circuit composed of a P-channel transistor whose source is connected to a terminal for receiving a supplied voltage and an N-channel transistor whose source is connected to a terminal for receiving a ground voltage, with the node between the drains of the two transistors used as the output terminal of the output circuit. A capacitive circuit element is connected between the sources of the two transistors, and thus in parallel with the output circuit, so as to suppress variations that occur in the current supplied from the supplied power as a result of a current being fed through the output circuit to or from a load connected to the output terminal. This helps keep constant the voltage that is supplied to an internal circuit that is connected in parallel with the output circuit, and thereby stabilize the operation of the internal circuit.

Abstract: A semiconductor device has a multiplicity of DAC channels for performing digital-to-analog conversion of video signals. Signal processing means for delaying processing of signals by a predetermined delay time is provided in at least one DAC channel. The signal processing means functions as a phase inversion means to reduce cross talks between the DAC channels. The signal processing means also functions as a delay circuit to reduce voltage fluctuations in the power supply.

Abstract: A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock. The frequency division ratios are distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.

Abstract: A semiconductor integrated circuit device has an output circuit composed of a P-channel transistor whose source is connected to a terminal for receiving a supplied voltage and an N-channel transistor whose source is connected to a terminal for receiving a ground voltage, with the node between the drains of the two transistors used as the output terminal of the output circuit. A capacitive circuit element is connected between the sources of the two transistors, and thus in parallel with the output circuit, so as to suppress variations that occur in the current supplied from the supplied power as a result of a current being fed through the output circuit to or from a load connected to the output terminal. This helps keep constant the voltage that is supplied to an internal circuit that is connected in parallel with the output circuit, and thereby stabilize the operation of the internal circuit.

Abstract: A self-contained game is provided wherein a player attempts to win one of a plurality of premiums displayed within the game. The game includes a premium-display space surrounded by a first plurality and second plurality of indicators. The indicators may be incandescent lamps. A controller is provided which is configured to sequentially distinguish and extinguish individual indicators comprising said first and second pluralities in a manner to give the appearance of a single indication traveling amongst said first and second plurality of indicators. A player may arrest the apparent motion of said traveling indication by actuating an interface device in an attempt to stop the indication at a selected position corresponding to one of the indicators comprising the second plurality of indicators. The controller is configured to determine which indicator was last distinguished at the time the interface was actuated, and whether the last distinguished indicator is a member of the second plurality.

Abstract: A scan converter converts horizontal and vertical synchronizing signals and digital R, G, and B signals fed from a computer into a television signal through digital processing that is performed by an encoder at a rate of 4.times.fsc (where fsc represents the frequency of the chrominance subcarrier of the television signal). The scan converter has a line memory which temporarily stores the digital signals from the computer to supply the digital signals to the encoder at the rate of 4.times.fsc.

Abstract: A signal processing apparatus has a clock generator that generates a clock in accordance with the rate at which picture elements are scanned. The clock generator includes a first frequency divider for dividing the output frequency of a voltage-controlled oscillator for generating the clock, a second frequency divider for dividing the output frequency of a reference frequency oscillator, a phase comparator for comparing phases between the outputs of the first and second frequency dividers, means for applying the output of the phase comparator to the reference frequency oscillator as a control signal, and a third frequency divider for performing voltage division on the output of the voltage-controlled oscillator to obtain the clock. The clock obtained has a frequency determined as: ##EQU1## where M, N, and P represent the frequency-division ratios of the first, second, and third frequency dividers, respectively, and f.sub.x represents the reference frequency.