Patents by Inventor Yasunori Kurosawa
Yasunori Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9139861Abstract: A cellulose gel medium having good visibility of microbial colonies, a cellulose gel culture substrate for manufacturing the cellulose gel medium, a method for manufacturing the cellulose gel culture substrate, a method for screening cellulase-producing microorganisms or cellulase activity with greater efficiency and rapidity, and a culture substrate, which includes a cellulose gel containing cellulose and water as medium-solidifying components, the cellulose has the viscosity of 12 to 35 mPa·S as measured at 26° C. with a solution prepared by dissolving the cellulose at a concentration of 2.5 mg/mL in dimethylacetamide containing 8% (W/V) lithium chloride.Type: GrantFiled: October 24, 2011Date of Patent: September 22, 2015Assignees: Japan Agency for Marine-Earth Science and Technology, Kyokuto Pharmaceutical Industrial Co., Ltd.Inventors: Kazunori Nagaki, Yasunori Kurosawa, Takuo Shiraishi, Shigeru Deguchi, Mikiko Tsudome
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Publication number: 20150050680Abstract: Providing is a new enzyme assay method for enzymes having a water-insoluble or substantially water-insoluble substrate. In the method for measuring enzymatic activity, a prescribed amount of an enzyme is disposed on a part of the surface of a gel comprising dispersoids, at least some of which are the substrate of the enzyme. Recesses formed in the surface of the gel by the action of the enzyme are measured, and the enzyme activity is calculated on the basis of the measurement results and the amount of the enzyme. The measurement of the recesses formed in the surface of the gel is performed using a method for measuring the shape and the volume of the recesses, a method for measuring changes in the optical transmittance of the gel due to the formation of the recesses, or a method for measuring changes in the optical reflectance of the gel surface due to the formation of the recesses.Type: ApplicationFiled: February 20, 2013Publication date: February 19, 2015Applicants: Japan Agency for Marine-Earth Science and Technology, Kyokuto Pharmaeutical Industrial Co., Ltd.Inventors: Shigeru Deguchi, Mikiko Tsudome, Kazunori Nagaki, Nemuri Todaka, Yasunori Kurosawa
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Publication number: 20130323768Abstract: A cellulose gel medium having good visibility of microbial colonies, a cellulose gel culture substrate for manufacturing the cellulose gel medium, a method for manufacturing the cellulose gel culture substrate, a method for screening cellulase-producing microorganisms or cellulase activity with greater efficiency and rapidity, and a culture substrate, which includes a cellulose gel containing cellulose and water as medium-solidifying components, the cellulose has the viscosity of 12 to 35 mPa·S as measured at 26° C. with a solution prepared by dissolving the cellulose at a concentration of 2.5 mg/mL in dimethylacetamide containing 8% (W/V) lithium chloride.Type: ApplicationFiled: October 24, 2011Publication date: December 5, 2013Applicants: Japan Agency for Marine-Earth Science and Technology, Kyokuto Pharmaceutical Industrial Co., Ltd.Inventors: Kazunori Nagaki, Yasunori Kurosawa, Takuo Shiraishi, Shigeru Deguchi, Mikiko Tsudome
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Patent number: 8143173Abstract: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer on the wiring line after step (b); and (d) forming a protective layer on a second surface opposite to the first surface of the semiconductor substrate after step (c).Type: GrantFiled: November 20, 2007Date of Patent: March 27, 2012Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 7981792Abstract: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in contact with the underlayer, and a second section which is not in contact with the underlayer.Type: GrantFiled: April 2, 2007Date of Patent: July 19, 2011Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 7615474Abstract: A method for manufacturing a semiconductor device includes (a) forming a conductive film on a first surface having an electrode of a semiconductor substrate having an integrated circuit formed therein, the electrode being electrically coupled to the integrated circuit, such that the electrode is covered, forming a plating resist layer on the conductive film such that the plating resist layer has an opening portion exposing part of the conductive film, and forming a metal layer on the exposed part from the plating resist layer of the conductive film by electrolytic plating, the electrolytic plating being performed by applying an electric current to the conductive film; (b) removing the plating resist layer after the step (a); (c) forming a resin layer on a second surface opposite to the first surface of the semiconductor substrate after the step (a); and (d) removing the exposed part from the metal layer of the conductive film by etching with the metal layer as a mask while etching a surface of the metal layerType: GrantFiled: November 20, 2007Date of Patent: November 10, 2009Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 7592244Abstract: A method of manufacturing a semiconductor device includes the step of forming a first insulating section with a protruding section on a semiconductor substrate, the step of forming a first conducting section on the first insulating section so as to pass on a surface of the protruding section, the step of forming a second insulating section for partially covering the first conducting section above the first insulating section so as to expose at least a part of the first conducting section formed on the surface of the protruding section, and the step of forming, on the second insulating section, a second conducting section electrically connected to the first conducting section via an exposed section of the first conducting section exposed from the second insulating section.Type: GrantFiled: April 3, 2006Date of Patent: September 22, 2009Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 7525193Abstract: A semiconductor device including: a semiconductor substrate having an electrode; a resin layer formed to avoid at least a part of the electrode; a land provided on the resin layer; an interconnect which electrically connects the electrode with the land; and an external terminal bonded to the land. The resin layer includes a first resin section which supports an end section of a bonding surface of the land bonded to the external terminal while avoiding a center section of the bonding surface, and a second resin section adjacent to the first resin section. The first resin section has a modulus of elasticity lower than a modulus of elasticity of the second resin section.Type: GrantFiled: May 13, 2005Date of Patent: April 28, 2009Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Publication number: 20080119037Abstract: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer on the wiring line after step (b); and (d) forming a protective layer on a second surface opposite to the first surface of the semiconductor substrate after step (c).Type: ApplicationFiled: November 20, 2007Publication date: May 22, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Yasunori KUROSAWA
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Publication number: 20080119045Abstract: A method for manufacturing a semiconductor device includes (a) forming a conductive film on a first surface having an electrode of a semiconductor substrate having an integrated circuit formed therein, the electrode being electrically coupled to the integrated circuit, such that the electrode is covered, forming a plating resist layer on the conductive film such that the plating resist layer has an opening portion exposing part of the conductive film, and forming a metal layer on the exposed part from the plating resist layer of the conductive film by electrolytic plating, the electrolytic plating being performed by applying an electric current to the conductive film; (b) removing the plating resist layer after the step (a); (c) forming a resin layer on a second surface opposite to the first surface of the semiconductor substrate after the step (a); and (d) removing the exposed part from the metal layer of the conductive film by etching with the metal layer as a mask while etching a surface of the metal layerType: ApplicationFiled: November 20, 2007Publication date: May 22, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Yasunori KUROSAWA
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Patent number: 7365429Abstract: A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring formed as to have a protruding portion projecting upwards on the resin layer, the wiring being electrically connected to the electrode; and a solder formed on the protruding portion of the wiring, wherein the upper face portion of the protruding portion is melt-eroded by the solder and the material of the protruding portion.Type: GrantFiled: August 4, 2005Date of Patent: April 29, 2008Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Publication number: 20070170566Abstract: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in contact with the underlayer, and a second section which is not in contact with the underlayer.Type: ApplicationFiled: April 2, 2007Publication date: July 26, 2007Applicant: SEIKO EPSON CORPORATIONInventor: Yasunori KUROSAWA
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Patent number: 7218008Abstract: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in contact with the underlayer, and a second section which is not in contact with the underlayer.Type: GrantFiled: June 29, 2004Date of Patent: May 15, 2007Assignee: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 7183645Abstract: A semiconductor device includes a semiconductor chip provided with an integrated circuit and a pad that is electrically connected to the integrated circuit. A wiring layer has a concave portion and is electrically connected to the pad. An external terminal is joined to the concave portion of the wiring layer. A resin layer is provided with a through hole and is disposed on the wiring layer. The through hole and the concave portion reside at the same position.Type: GrantFiled: March 17, 2004Date of Patent: February 27, 2007Assignee: Seiko Epson CorporationInventors: Yasunori Kurosawa, Terunao Hanaoka
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Publication number: 20060223303Abstract: A method of manufacturing a semiconductor device includes the step of forming a first insulating section with a protruding section on a semiconductor substrate, the step of forming a first conducting section on the first insulating section so as to pass on a surface of the protruding section, the step of forming a second insulating section for partially covering the first conducting section above the first insulating section so as to expose at least a part of the first conducting section formed on the surface of the protruding section, and the step of forming, on the second insulating section, a second conducting section electrically connected to the first conducting section via an exposed section of the first conducting section exposed from the second insulating section.Type: ApplicationFiled: April 3, 2006Publication date: October 5, 2006Inventor: Yasunori Kurosawa
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Patent number: 7067929Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a wiring layer on a semiconductor substrate having an integrated circuit and a pad electrically connected to the integrated circuit, the wiring layer being electrically connected to the pad, (b) forming a resin layer covering the wiring layer, (c) forming a first concave portion at an area of the resin layer, the area overlapping the wiring layer, by a first process, (d) forming a through-hole in the resin layer by removing a bottom of the first concave portion by a second process, the second process differing from the first process, and forming a second concave portion in the wiring layer in such a way that an angle between an osculating plane at any point of a surface of the second concave portion and a top surface of the wiring layer, with the angle being defined outside the second concave portion is 90° or more and (e) providing an external terminal in the second concave portion of the wiring layer.Type: GrantFiled: March 15, 2004Date of Patent: June 27, 2006Assignee: Seiko Epson CorporationInventors: Terunao Hanaoka, Yasunori Kurosawa
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Publication number: 20060049518Abstract: A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring formed as to have a protruding portion projecting upwards on the resin layer, the wiring being electrically connected to the electrode; and a solder formed on the protruding portion of the wiring, wherein the upper face portion of the protruding portion is melt-eroded by the solder and the material of the protruding portion.Type: ApplicationFiled: August 4, 2005Publication date: March 9, 2006Inventor: Yasunori Kurosawa
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Publication number: 20050263882Abstract: A semiconductor device including: a semiconductor substrate having an electrode; a resin layer formed to avoid at least a part of the electrode; a land provided on the resin layer; an interconnect which electrically connects the electrode with the land; and an external terminal bonded to the land. The resin layer includes a first resin section which supports an end section of a bonding surface of the land bonded to the external terminal while avoiding a center section of the bonding surface, and a second resin section adjacent to the first resin section. The first resin section has a modulus of elasticity lower than a modulus of elasticity of the second resin section.Type: ApplicationFiled: May 13, 2005Publication date: December 1, 2005Applicant: Seiko Epson CorporationInventor: Yasunori Kurosawa
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Patent number: 6894394Abstract: A method for manufacturing a semiconductor device includes (a) forming electrical interconnections over a surface of a semiconductor substrate having integrated circuits, (b) providing a plurality of bonding pads disposed on the surface of the semiconductor substrate, (c) electrically connecting the electrical connections to respective bonding pads of the plurality of bonding pads, (d) electrically connecting the plurality of bonding pads to each of the integrated circuits, (e) forming resin layers so as to cover the electrical interconnections, (f) forming concave portions by a first process, each of the concave portions being disposed in a corresponding portion of the resin layers that cover the electrical interconnections, (g) curing the resin layers having the concave portion, (h) forming through-holes by removing bottoms of the concave portions by a second process that differs from the first process and (i) forming external connection terminals, each being disposed on a corresponding area of the electricType: GrantFiled: March 15, 2004Date of Patent: May 17, 2005Assignee: Seiko Epson CorporationInventors: Terunao Hanaoka, Yasunori Kurosawa
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Publication number: 20050012209Abstract: A semiconductor device includes a semiconductor chip provided with an integrated circuit and a pad that is electrically connected to the integrated circuit. A wiring layer has a concave portion and is electrically connected to the pad. An external terminal is joined to the concave portion of the wiring layer. A resin layer is provided with a through hole and is disposed on the wiring layer. The through hole and the concave portion reside at the same position.Type: ApplicationFiled: March 17, 2004Publication date: January 20, 2005Inventors: Yasunori Kurosawa, Terunao Hanaoka