Patents by Inventor Yasunori Kuwasima

Yasunori Kuwasima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5587683
    Abstract: A booster circuit device comprises: a liquid crystal drive circuit (14) whose dissipated current changes; a timing circuit (11) for outputting a select signal according to the dissipated current of the liquid crystal drive circuit; a drive signal select circuit (12) for selecting and outputting any one of at least two drive signals CLK of different frequencies on the basis of the select signal outputted by the timing circuit (11); and a booster circuit (13) for supplying a supply voltage to the liquid crystal drive circuit (14) on the basis of the drive signal CLK outputted by the drive signal select circuit (12). Since any of the drive signals CLK of different frequencies can be selected and applied to the booster circuit (13) according to the dissipated current of the liquid crystal drive circuit (14), it is possible to reduce the current dissipation of the booster circuit, that is the current dissipation of the whole booster circuit device can be reduced markedly.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: December 24, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kawasaki, Yasunori Kuwasima, Hidehiko Tachibana, Syuji Katsuki, Akihiro Sueda
  • Patent number: 5016263
    Abstract: A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of the sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: May 14, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Kitagawa, Akihiro Sueda, Yasunori Kuwasima