Patents by Inventor Yasunori Nakano
Yasunori Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916112Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.Type: GrantFiled: August 8, 2019Date of Patent: February 27, 2024Assignee: ROHM CO., LTD.Inventors: Yasuhiro Kawakami, Yuki Nakano, Masaya Ueno, Seiya Nakazawa, Sawa Haruyama, Yasunori Kutsuma
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Patent number: 10718329Abstract: A scroll compressor is provided which includes: a revolving scroll, a fixed scroll, an autorotation preventing mechanism, a frame, a crank shaft provided with an eccentric pin portion which is eccentric with respect to an axis, the crank shaft being provided with a flange portion at a lower portion of the eccentric pin portion, the flange portion being larger than the diameter of the eccentric pin portion, a balance weight mounted on the flange portion, a sealing member performing sealing between the revolving scroll and the flange portion, and a thrust bearing arranged between the frame and the flange portion. The scroll compressor reduces the amount of oil flowing into a back pressure chamber, thereby improving the performance of the scroll compressor.Type: GrantFiled: May 13, 2016Date of Patent: July 21, 2020Assignee: HITACHI-JOHNSON CONTROLS AIR CONDITIONG, INC.Inventors: Yasunori Nakano, Satoshi Nakamura, Takamasa Adachi, Masatsugu Chikano, Yuuichi Yanagase
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Patent number: 10240601Abstract: A scroll compressor has a sealed container inside which a working fluid is sealed; a frame fixed inside the sealed container; a fixed scroll provided with a fixed-side spiral body formed in a spiral shape on a fixed-side base plate fixed inside the sealed container; and a revolving scroll in which a revolving-side spiral body meshing with the fixed-side spiral body is provided on a revolving-side base plate. The frame includes a first welded point at which the frame is fixed by welding to the sealed container, and a revolving-scroll-receiving surface supports a bottom surface of the revolving-side base plate opposite to a surface thereof on which the revolving-side spiral body is provided. A frame outer peripheral groove provided in an outer periphery of the frame faces an inner periphery of the sealed container between the revolving-scroll-receiving surface and the first welded point.Type: GrantFiled: October 27, 2014Date of Patent: March 26, 2019Assignee: Hitachi-Johnson Controls Air Conditioning, Inc.Inventors: Yasunori Nakano, Shuji Hasegawa, Satoshi Nakamura
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Publication number: 20180128269Abstract: A scroll compressor is provided which includes: a revolving scroll, a fixed scroll, an autorotation preventing mechanism, a frame, a crank shaft provided with an eccentric pin portion which is eccentric with respect to an axis, the crank shaft being provided with a flange portion at a lower portion of the eccentric pin portion, the flange portion being larger than the diameter of the eccentric pin portion, a balance weight mounted on the flange portion, a sealing member performing sealing between the revolving scroll and the flange portion, and a thrust bearing arranged between the frame and the flange portion. The scroll compressor reduces the amount of oil flowing into a back pressure chamber, thereby improving the performance of the scroll compressor.Type: ApplicationFiled: May 13, 2016Publication date: May 10, 2018Inventors: Yasunori NAKANO, Satoshi NAKAMURA, Takamasa ADACHI, Masatsugu CHIKANO, Yuuichi YANAGASE
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Publication number: 20170306951Abstract: A scroll compressor includes a fixed scroll and an orbiting scroll and causes the orbiting scroll to perform an orbiting motion to form a suction chamber and a compression chamber. The scroll compressor includes a first space in a back surface center of the orbiting scroll, lubricant in a bottom of a sealed container, a second space provided further on an outer circumference side than the first space on a back surface of the orbiting scroll, a first oil leak path for causing a part of oil in the first space to leak to the second space, an oil return passage for returning most of the oil in the first space to the bottom in the sealed container, a second oil leak path for causing a part of the oil in the second space to leak to the suction chamber, and a third oil leak path.Type: ApplicationFiled: September 29, 2015Publication date: October 26, 2017Inventors: Masatsugu CHIKANO, Masaru OHTAHARA, Satoshi NAKAMURA, Syuuji HASEGAWA, Yasunori NAKANO, Isamu TSUBONO
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Publication number: 20160348677Abstract: An object of the present invention is to improve reliability in a scroll compressor in which a frame is fixed by welding.Type: ApplicationFiled: October 27, 2014Publication date: December 1, 2016Inventors: Yasunori NAKANO, Shuji HASEGAWA, Satoshi NAKAMURA
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Patent number: 6614190Abstract: A wafer holder for holding a wafer includes a wafer holder base, a wafer fixing part, holder pins, a bearing, a housing, and a coil spring. The wafer fixing part is fixed to an outer circumference of a wafer holder. The holder pins are arranged to face the wafer fixing part. The holder pin is rotatably supported by the bearing. The holder pins are movably supported along the diameter direction of the wafer holder base by the coil spring. In the process of holding a side of the wafer with the holder pins, when force from the wafer works on the holder pins, the holder pins are rotated with a Z axis as a center, thus reducing frictional force between the holder pin and the wafer. Accordingly, it is possible to prevent particle generation from holding an implanting object.Type: GrantFiled: August 28, 2001Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Tomita, Kazuo Mera, Isao Hashimoto, Yasunori Nakano, Takayoshi Seki
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Publication number: 20020105277Abstract: A wafer holder for holding a wafer includes a wafer holder base, a wafer fixing part, holder pins, a bearing, a housing, and a coil spring. The wafer fixing part is fixed to an outer circumference of a wafer holder. The holder pins are arranged to face the wafer fixing part. The holder pin is rotatably supported by the bearing. The holder pins are movably supported along the diameter direction of the wafer holder base by the coil spring. In the process of holding a side of the wafer with the holder pins, when force from the wafer works on the holder pins, the holder pins are rotated with a Z axis as a center, thus reducing frictional force between the holder pin and the wafer. Accordingly, it is possible to prevent particle generation from holding an implanting object.Type: ApplicationFiled: August 28, 2001Publication date: August 8, 2002Inventors: Hiroyuki Tomita, Kazuo Mera, Isao Hashimoto, Yasunori Nakano, Takayoshi Seki
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Patent number: 5804868Abstract: A highly reliable semiconductor device having a planar junction, which comprises a main junction and a plurality of field limiting ring regions surrounding the main junction, and an electrically floating conductive layer to completely cover that part of the surface of an n.sup.- layer between the main junction and the nearest field limiting ring region thereto through an insulating layer to suppress influences by external factors such as charged particles, etc. In accordance with such a structured device, when a voltage for making the main junction into a reverse bias state is applied, the potential of the conductive layer becomes fixed to an intermediate potential between the main junction and the nearest field limiting ring region thereto and plays a role of shield effect. In fact, even if the device is incorporated into a resin-sealed package and subjected to reliability tests (high temperature DC reverse bias tests), the breakdown voltage is not changed at all.Type: GrantFiled: February 13, 1996Date of Patent: September 8, 1998Assignee: Hitachi, Ltd.Inventors: Hideo Kobayashi, Mutsuhiro Mori, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5670811Abstract: The present invention is directed to a semiconductor device which can achieve high current density and which has a high reliability. In the insulated gate semiconductor device according to the present invention, a plurality of insulating gates are provided, with each two adjacent insulating gates being spaced from each other, the insulating gates being provided on a second semiconductor region of a first conductivity type. A first semiconductor region, of the same or different conductivity type from that of the second semiconductor region, extends from a surface of the second semiconductor region opposed to the surface thereof having the insulating gates thereon. A plurality of third semiconductor regions are provided in the second semiconductor region, between the insulating gates and aligned therewith, and two fourth semiconductor regions are provided extending into each of the third semiconductor regions, aligned with the sides of adjacent insulating gates.Type: GrantFiled: April 28, 1995Date of Patent: September 23, 1997Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Tomoyuki Tanaka, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5285094Abstract: The present invention relates to a semiconductor device having an n-type semiconductor region forming one of the main surfaces of a semiconductor substrate, with a plurality of p-type semiconductor regions formed in the n-type semiconductor region. Two exposed n-type semiconductor regions are formed on each of the p-type semiconductor regions, with a main electrode formed on the n-type semiconductor regions and the exposed p-type semiconductor region therebetween. An insulated gate extends from one of the n-type semiconductor regions in one of the p-type semiconductor regions to a closer one of the n-type semiconductor regions in an adjacent p-type semiconductor region. The length of the insulated gate is longer than a distance between adjacent insulated gates.Type: GrantFiled: July 29, 1992Date of Patent: February 8, 1994Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Tomoyuki Tanaka, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5262339Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.Type: GrantFiled: February 10, 1993Date of Patent: November 16, 1993Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5208471Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type formed on said semiconductor substrate, a first semiconductor well region of a second conductivity type and second semiconductor well regions of the second conductivity type, the latter two types of regions being formed in said semiconductor layer. The first semiconductor well region is located at the peripheral area of the semiconductor, and the well is deeper than the well of the second semiconductor well regions. Third semiconductor well regions of the first conductivity type are formed in the second semiconductor well regions. Gate electrodes and an emitter (source) electrode are formed at specified positions on the upper surface of the semiconductor device, and a collector (drain) electrode is formed on the bottom surface.Type: GrantFiled: September 19, 1991Date of Patent: May 4, 1993Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5179034Abstract: A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.30 -source layer.Type: GrantFiled: April 11, 1991Date of Patent: January 12, 1993Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Tomoyuki Tanaka, Yasumichi Yasuda, Yasunori Nakano
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Patent number: 5032532Abstract: A method for fabricating an insulated gate semiconductor device comprises the steps of forming insulated gates on an n.sup.- -layer surface, forming p-well layers in the n.sup.- -layer using the insulated gates as masks, forming phosphosilicate glass layers on the side walls of the insulated gates and diffusing the impurities from the phosphosilicate glass layers into the p-well layers to form n.sup.+ -source layer.Type: GrantFiled: August 17, 1988Date of Patent: July 16, 1991Assignee: Hitachi, Ltd.Inventors: Mutsuhiro Mori, Tomoyuki Tanaka, Yasumichi Yasuda, Yasunori Nakano
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Patent number: D1021831Type: GrantFiled: September 20, 2021Date of Patent: April 9, 2024Assignee: ROHM CO., LTD.Inventors: Yuki Nakano, Kenji Yamamoto, Yasunori Kutsuma