Patents by Inventor Yasunori Narizuka

Yasunori Narizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8357933
    Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
  • Patent number: 8206997
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Patent number: 8062911
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Publication number: 20110281380
    Abstract: Provided is a probe card for LSI inspection that can achieve electrical conduction to electrodes on an LSI with a low load without damaging the electrodes and a structural body therebelow, even if the electrodes are arranged at a narrow pitch and in a complex manner. A contact terminal is formed in a truncated square pyramidal recess provided on a film-shaped probe. A dent is often formed on a surface of the film-shaped probe just above the contact terminal. A resin coating film is formed so as to eliminate the dent and flatten the surface of the film-shaped probe. At this time, it is preferred that an amount of cure shrinkage of a resin paste for forming the resin coating film is 0.1% or less.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 17, 2011
    Inventors: Yasunori NARIZUKA, Etsuko Takane, Akio Hasebe
  • Publication number: 20110175634
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: March 30, 2011
    Publication date: July 21, 2011
    Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20110136272
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: February 1, 2011
    Publication date: June 9, 2011
    Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
  • Patent number: 7901958
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: March 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20110014727
    Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
    Type: Application
    Filed: September 16, 2010
    Publication date: January 20, 2011
    Inventors: Akira YABUSHITA, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
  • Publication number: 20100301884
    Abstract: A semiconductor chip inspection apparatus largely reduces occurrence of damage due to foreign matter in an inspection process and improves durability at the same time of miniaturization is provided. As to a highly accurate thin-film probe sheet which performs: a contact to electrode pads arranged at a narrow pitch and a high density along with integration of semiconductor chip; and an inspection of semiconductor chips, by providing two layers of metal films selectively removable in a step-like shape in a periphery region of fine contact terminal having sharp tips and arranged at a high density and a narrow pitch at the same level as electrode pads, an upper periphery of the contact terminals is covered with an insulating film, and a large space region is formed.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 2, 2010
    Inventors: Etsuko Takane, Yasunori Narizuka, Akira Yabushita, Kenji Kawakami, Akio Hasebe
  • Publication number: 20100304510
    Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 2, 2010
    Inventors: Masayoshi OKAMOTO, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
  • Publication number: 20100279502
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Application
    Filed: July 15, 2010
    Publication date: November 4, 2010
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Publication number: 20100277192
    Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 4, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Akio HASEBE, Hideyuki MATSUMOTO, Shingo YORISAKI, Yasuhiro MOTOYAMA, Masayoshi OKAMOTO, Yasunori NARIZUKA, Naoki OKAMOTO
  • Patent number: 7776626
    Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 17, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
  • Patent number: 7724006
    Abstract: A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Yasunori Narizuka
  • Patent number: 7656174
    Abstract: A manufacturing method of a semiconductor device employing a semiconductor inspection apparatus to accurately inspect semiconductor elements while still in the wafer state, the semiconductor inspection apparatus including: a probe sheet 31 having contact terminals 7 which contact electrodes 3 of a wafer 1 and contact bumps 20b electrically connected to respective contact terminals 7; and a probe sheet 34 which is backed by a metal film 30b and having contact electrodes 34a which contact the contact bumps 20b of the probe sheet 31 and peripheral electrodes 27b electrically connected to the respective contact electrodes 34a, the wafer 1 is interposed between the probe sheet 34 and the supporting member 33 via the probe sheet 31 by reducing pressure through vacuuming, and the contact terminals 7 which have a pyramidal or truncated shape are contacted to the electrodes 3 of the wafer 1 at a desired atmospheric pressure, thereby performing the inspection.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Yasunori Narizuka
  • Patent number: 7598100
    Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: October 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka
  • Publication number: 20090212798
    Abstract: A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time.
    Type: Application
    Filed: October 17, 2008
    Publication date: August 27, 2009
    Inventors: Susumu KASUKABE, Yasunori Narizuka
  • Patent number: 7537943
    Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 26, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura
  • Publication number: 20090130785
    Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 21, 2009
    Inventors: Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka
  • Patent number: 7534629
    Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Motoji Murakami, Masayoshi Okamoto, Yasunori Narizuka, Susumu Kasukabe