Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.

Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.

Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.

Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.

Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.

Abstract: The present invention relates to a power semiconductor device which includes: a first conductivity-type silicon carbide semiconductor layer; a switching device which is formed on the silicon carbide semiconductor layer; a second conductivity-type electric field relaxation impurity region which is formed in a terminal portion of a formation region of the switching device and which relaxes an electric field of the terminal portion; and a first conductivity-type added region which is provided between second conductivity-type well regions of a plurality of unit cells that constitutes the switching device, and at least on an outer side of the electric field relaxation impurity region, and which has an impurity concentration higher than that in the silicon carbide semiconductor layer.

Abstract: The present invention relates to a power semiconductor device which includes: a first conductivity-type silicon carbide semiconductor layer; a switching device which is formed on the silicon carbide semiconductor layer; a second conductivity-type electric field relaxation impurity region which is formed in a terminal portion of a formation region of the switching device and which relaxes an electric field of the terminal portion; and a first conductivity-type added region which is provided between second conductivity-type well regions of a plurality of unit cells that constitutes the switching device, and at least on an outer side of the electric field relaxation impurity region, and which has an impurity concentration higher than that in the silicon carbide semiconductor layer.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Abstract: A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region.

Abstract: An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

Abstract: An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.