Abstract: When a main video data stream that is selected and decoded is changed, a video data processing device 101 instructs, via a network 110, a surveillance camera that encodes a newly-selected main video data stream to create a main video data stream with a smaller I-frame interval as of that point, and instructs, via a network 110, a surveillance camera that encodes a newly-deselected main video data stream to create a main video data stream with a larger I-frame interval as of that point.

Abstract: A PLL controller for controlling the tracking rate of a phase-locked loop (PLL), in particular, controlling coefficients to be input to a device such as a multiplier of the phase-locked loop. A PLL controller receives a phase error between a horizontal sync signal in a video signal and a reference signal. Then an error amount detector measures the phase error using the N thresholds to output a control signal indicating any of N+1 levels. A coefficient selector outputs one of the N+1 gains as a coefficient signal, the one gain corresponding to the level indicated by the control signal, so that the tracking rate of the phase-locked loop is controlled in response to the input video signal, and thus a high-quality video image with less jitter can be provided.

Abstract: A YC separator circuit which is capable of achieving YC separation at a high accuracy. The YC separator circuit comprises line memories, bandpass filters, an edge detector circuit, a color correlation determining circuit, and a YC separation filter circuit. The YC separator circuit separates a C signal from a composite signal using a two-line comb filter or a three-line comb filter. The subtractor subtracts the C signal separated by the YC separation filter circuit from the composite signal to separate a Y signal. A trap filter is a frequency filter for dividing a Y signal from a composite signal. A luminance correlation determining circuit calculates a difference between the Y signals received from the subtractor and trap filter, and outputs the Y signal separated by the subtractor when the difference is larger than a predetermined value, and outputs the Y signal separated by the trap filter when the difference is smaller than the predetermined value.

Abstract: A PLL controller for controlling the tracking rate of a phase-locked loop (PLL), in particular, controlling coefficients to be input to a device such as a multiplier of the phase-locked loop. A PLL controller receives a phase error between a horizontal sync signal in a video signal and a reference signal. Then an error amount detector measures the phase error using the N thresholds to output a control signal indicating any of N+1 levels. A coefficient selector outputs one of the N+1 gains as a coefficient signal, the one gain corresponding to the level indicated by the control signal, so that the tracking rate of the phase-locked loop is controlled in response to the input video signal, and thus a high-quality video image with less jitter can be provided.

Abstract: The delay circuit composed of plural flip-flops converts an input data into plural data 110-0˜110-n having delays of 1˜n clocks, which are inputted to the selector of the selector circuit. The counter counts the pixel number per one line of the input data, and supplies a discrete value signal indicating the counted pixel number to the judgment circuit of the selector. The judgment circuit calculates a difference between the standard pixel number and the pixel number that the discrete value signal indicates, and calculates a new delay to the delay circuit on the basis of this calculated difference. The selector outputs an output data based on the new delay calculated. With a simplified circuit configuration as above, the pixel number for each line will be regulated into the standard pixel number.

Abstract: A YC separator circuit which is capable of achieving YC separation at a high accuracy. The YC separator circuit comprises line memories, bandpass filters, an edge detector circuit, a color correlation determining circuit, and a YC separation filter circuit. The YC separator circuit separates a C signal from a composite signal using a two-line comb filter or a three-line comb filter. The subtractor subtracts the C signal separated by the YC separation filter circuit from the composite signal to separate a Y signal. A trap filter is a frequency filter for dividing a Y signal from a composite signal. A luminance correlation determining circuit calculates a difference between the Y signals received from the subtractor and trap filter, and outputs the Y signal separated by the subtractor when the difference is larger than a predetermined value, and outputs the Y signal separated by the trap filter when the difference is smaller than the predetermined value.

Abstract: An image processing apparatus includes a memory circuit, one-line judging circuit, a write control circuit and a read control circuit. The memory circuit stores an input data in response to a write address and outputs an output data in response to a read address. The one-line judging circuit receives a horizontal synchronization signal and a sampling clock signal and compares a number of pixels sampled within one line of the horizontal synchronization signal with a predetermined number so as to output a comparison signal and a difference signal representing a difference between the sampled number and a predetermined number. The write control circuit generates the write address in response to the clock signal and the comparison signal, and a read control signal in response to the comparison signal. The read control circuit generates the read address in response to the write address, the read control signal and the difference signal.

Abstract: The decoder for separation of Y (luminance) signals and C (color) signals from composite signals includes a correlation judging section. It is adapted to judge whether there is line correlation among neighboring signal lines including a signal line to be separated during each of the horizontal scanning intervals. A stripe component judging section is adapted to judge whether an image having vertical stripes is contained in the composite signal. A filter section having first and second filters is used selectively depending on correlation results, and a selecting section is adapted to output a signal to select one of filters in accordance with judgment results from both judging sections. The decoder is capable of preventing decreases in resolution in images having vertical stripes.

Abstract: An image processing apparatus includes a memory circuit, one-line judging circuit, a write control circuit and a read control circuit. The memory circuit stores an input data in response to a write address and outputs an output data in response to a read address. The one-line judging circuit receives a horizontal synchronization signal and a sampling clock signal and compares a number of pixels sampled within one line of the horizontal synchronization signal with a predetermined number so as to output a comparison signal and a difference signal representing a difference between the sampled number and a predetermined number. The write control circuit generates the write address in response to the clock signal and the comparison signal, and a read control signal in response to the comparison signal. The read control circuit generates the read address in response to the write address, the read control signal and the difference signal.

Abstract: A luminance (Y) and a color difference (C) signal separator switches filters according to an image and separates a Y signal and a C signal included in a composite color picture signal to eliminate a degradation which would otherwise be involved at a transition point because of the characteristics of the filters. A first weighting circuit calculates the weighted average of the C signals extracted from the composite signal by a comb filter and a three-line comb filter. A second weighting circuit calculates the weighted average of the C signals extracted by the three-line comb filter and a two-line comb filter. When the motion level of the image exceeds a predetermined threshold, a selector selects, as the final C signal, the signal output from the second weighting circuit. When the motion level is equal to or lower than the predetermined threshold, the selector selects, as the final C signal, the signal output from the first weighting circuit.

Abstract: The delay circuit composed of plural flip-flops converts an input data into plural data 110-0˜110-n having delays of 1˜n clocks, which are inputted to the selector of the selector circuit. The counter counts the pixel number per one line of the input data, and supplies a discrete value signal indicating the counted pixel number to the judgment circuit of the selector. The judgment circuit calculates a difference between the standard pixel number and the pixel number that the discrete value signal indicates, and calculates a new delay to the delay circuit on the basis of this calculated difference. The selector outputs an output data based on the new delay calculated. With a simplified circuit configuration as above, the pixel number for each line will be regulated into the standard pixel number.

Abstract: A decoder for composite video signals is provided which is capable of preventing decreases in resolution at a time of YC (Luminance and color signals) separation from composite signals indicating images having vertical stripes.

Abstract: In a method for managing a skill of a learner, it is determined based on an obtained date when the learner obtained the skill, whether or not the skill obtained by the learner passes a valid term, and a skill level is changed based on a result.