Abstract: A successive approximation type analog-to-digital (AD) converter includes: a converting and comparing section configured to compare an input analog signal and an analog signal as an analog conversion result of a digital data; and a successive approximation section configured to change the digital data based on the comparison result by the converting and comparing section. The converting and comparing section includes: a DA (digital-to-analog) section configured to perform an analog conversion on the digital data of a predetermined number of bits in an ordinary mode, and on the digital data of bits smaller than the predetermined number of bits in a test mode.

Abstract: A semiconductor device includes a test target circuit subjected to self-diagnosis, a PLL circuit that outputs a clock for the self-diagnosis to the test target circuit, a diagnostic register that stores a clock frequency corresponding to an operation speed limit of the test target circuit, and a control circuit that sets a frequency of the clock output from the clock circuit based on the clock frequency stored in the diagnostic register when executing the self-diagnosis.

Abstract: A successive approximation type analog-to-digital (AD) converter includes: a converting and comparing section configured to compare an input analog signal and an analog signal as an analog conversion result of a digital data; and a successive approximation section configured to change the digital data based on the comparison result by the converting and comparing section. The converting and comparing section includes: a DA (digital-to-analog) section configured to perform an analog conversion on the digital data of a predetermined number of bits in an ordinary mode, and on the digital data of bits smaller than the predetermined number of bits in a test mode.

Abstract: A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.

Abstract: A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.

Abstract: An interface circuit effectively prevents ringing of signal waveform. In a buffer integrated circuit, a level of an input signal to an input buffer and a reference level are compared by a comparator. A transistor is operated to be turned ON and OFF depending upon the comparison result to control level of the input signal. Even when the ringing of the waveform from the output buffer is large, ringing may not be recognized as “H” level signal so as not to cause malfunction.

Abstract: An output buffer includes a p-channel transistor, and first and second n-channel transistors. The p-channel transistor has one of a source and drain which is connected to power supply and the other which is connected to an output node connected to an output terminal. The first n-channel transistor has one of a source and drain which is grounded and the other which is connected to the output node. The second n-channel transistor is series-connected to the p-channel transistor between a power supply and the output node and receives at a gate a power supply potential level which rises at substantially the same time as the power supply upon ON operation.

Abstract: A microprogram controlled data processing system includes an instruction controller receiving a given instruction code for generating a micro address, a micro ROM receiving the micro address for generating a set of micro codes corresponding to the given instruction code, a micro decoder receiving the set of micro codes for generating a predetermined series of microorders, and a runaway detecting circuit for monitoring the order of execution of the series of microorders and generating an abnormal signal on the basis of the result of the monitoring.

Abstract: A semi-flash type analog/digital converter for eliminating errors in its output signals which are caused by noise. The analog/digital converter includes a D/A converter for outputting a plurality of analog signals which are produced based on a plurality of input signals. A plurality of comparators compare the voltage of an analog input signal, provided via a sample and hold circuit, with the analog signals output from the D/A converter. The output from the comparators are supplied to two latches, which further provide the outputs to a plurality of encoders. One of the encoders encodes the signals provided by one of the latches and outputs signals representative of high order bits of a digital signal. A second encoder, which encodes output signals provided by the other latch, is a correction encoder. The correction encoder corrects the signals provided by the latch if it determines that any of the signals are in error, and outputs signals representing the lower order bits of a digital output signal.