Abstract: A clock signal analysis device (100, 200, 300) has a pre-processing section (4) for reading circuit connection information, transistor characteristic information, and control information stored in memories (1, 2, 3) and for editing those information to be used for a simulation by a simulation execution section (5). The simulation execution section (5) executes a simulation of circuit operation, and then an after-processing section (6) calculates a delay value from a clock signal input node to a clock signal terminal node, a difference between delay values of clock signal terminal nodes, a rising time, a falling time of the clock signal and displays an analysis result by using a two-dimensional distribution map through a monitor (8).

Abstract: A simulator includes a timing simulation section executing timing simulation for a logic circuit of an electronic component, a time management section extracting logical operation time at an output terminal of the electronic component from a result of the simulation, a transmission line simulation section executing simulation of a transmission line connected to the output terminal from the logical operation time extracted by the time management section, and a simulation result processing section combining the result of the simulation by the timing simulation section and a result of the transmission line simulation by the transmission line simulation section.

Abstract: A circuit connection information generating device for generating circuit connection information which correctly reflects circuit connection information provided from a circuit drawing and which contains parasitic elements is disclosed.