Patents by Inventor Yasunori Terashima

Yasunori Terashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7953014
    Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: May 31, 2011
    Assignees: National Institute of Advanced Industrial Science and Technology, DUAXES Corporation, BITS Co., Ltd.
    Inventors: Kenji Toda, Toshihiro Katashita, Kazumi Sakamaki, Takeshi Inui, Mitsugu Nagoya, Yasunori Terashima
  • Patent number: 7590916
    Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: September 15, 2009
    Inventors: Toshihiro Katashita, Kenji Toda, Kazumi Sakamaki, Takeshi Inui, Tadamasa Takayama, Mitsugu Nagoya, Yasunori Terashima
  • Publication number: 20070136411
    Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.
    Type: Application
    Filed: June 9, 2006
    Publication date: June 14, 2007
    Inventors: Toshihiro Katashita, Kenji Toda, Kazumi Sakamaki, Takeshi Inui, Tadamasa Takayama, Mitsugu Nagoya, Yasunori Terashima
  • Publication number: 20070067130
    Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.
    Type: Application
    Filed: March 7, 2006
    Publication date: March 22, 2007
    Inventors: Kenji Toda, Toshihiro Katashita, Kazumi Sakamaki, Takeshi Inui, Mitsugu Nagoya, Yasunori Terashima
  • Patent number: 5407752
    Abstract: A polyester resin comprising units of a dicarboxylic acid component composed mainly of an aromatic dicarboxylic acid or its ester forming derivative and a diol component composed mainly of ethylene glycol and an ethylene oxide adduct of a bisphenol compound or its derivative.The resin may advantageously be used as a molding material for various moldings such as extrusion molding, blow molding, vacuum molding and injection molding.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: April 18, 1995
    Assignee: Mitsubishi Rayon Company Ltd.
    Inventors: Tatsushi Fukuzumi, Noriyuki Tajiri, Miki Murata, Yasunori Terashima, Tomohiko Yoshida