Patents by Inventor Yasunori Uchino

Yasunori Uchino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840130
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 10546773
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20190385905
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20180204766
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 9947575
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 17, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20160254184
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 9368430
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: June 14, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20140367861
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 18, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 7557446
    Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
  • Publication number: 20080303171
    Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 11, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
  • Patent number: 7432180
    Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 7, 2008
    Assignee: Fujitsu Limited
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Patent number: 7429525
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: September 30, 2008
    Assignee: Fujitsu Limited
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Patent number: 7407888
    Abstract: A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: August 5, 2008
    Assignee: Fujitsu Limited
    Inventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
  • Publication number: 20070166975
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.
    Type: Application
    Filed: May 16, 2006
    Publication date: July 19, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Publication number: 20070166974
    Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.
    Type: Application
    Filed: May 16, 2006
    Publication date: July 19, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
  • Publication number: 20060284317
    Abstract: A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.
    Type: Application
    Filed: February 17, 2006
    Publication date: December 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura