Patents by Inventor Yasunori Uchino
Yasunori Uchino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840130Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: GrantFiled: August 27, 2019Date of Patent: November 17, 2020Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Patent number: 10546773Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: GrantFiled: March 13, 2018Date of Patent: January 28, 2020Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Publication number: 20190385905Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Publication number: 20180204766Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: ApplicationFiled: March 13, 2018Publication date: July 19, 2018Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Patent number: 9947575Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: GrantFiled: May 11, 2016Date of Patent: April 17, 2018Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Publication number: 20160254184Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Yasunori Uchino, Kenichi Watanabe
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Patent number: 9368430Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: GrantFiled: June 2, 2014Date of Patent: June 14, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Publication number: 20140367861Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.Type: ApplicationFiled: June 2, 2014Publication date: December 18, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasunori Uchino, Kenichi Watanabe
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Patent number: 7557446Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: GrantFiled: June 30, 2008Date of Patent: July 7, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
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Publication number: 20080303171Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: ApplicationFiled: June 30, 2008Publication date: December 11, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
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Patent number: 7432180Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.Type: GrantFiled: May 16, 2006Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
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Patent number: 7429525Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.Type: GrantFiled: May 16, 2006Date of Patent: September 30, 2008Assignee: Fujitsu LimitedInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
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Patent number: 7407888Abstract: A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: GrantFiled: February 17, 2006Date of Patent: August 5, 2008Assignee: Fujitsu LimitedInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura
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Publication number: 20070166975Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.Type: ApplicationFiled: May 16, 2006Publication date: July 19, 2007Applicant: FUJITSU LIMITEDInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
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Publication number: 20070166974Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.Type: ApplicationFiled: May 16, 2006Publication date: July 19, 2007Applicant: FUJITSU LIMITEDInventors: Yasunori Uchino, Kazuo Kawamura, Naoyoshi Tamura
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Publication number: 20060284317Abstract: A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.Type: ApplicationFiled: February 17, 2006Publication date: December 21, 2006Applicant: FUJITSU LIMITEDInventors: Takeshi Ito, Satoshi Inagaki, Yasunori Uchino, Kazuo Kawamura