Abstract: An information terminal including a housing projection section which is provided at a position shifted to one end side of a terminal main body in a longitudinal direction while projecting in a thickness direction of the terminal main body, and in which a device is housed, and an expansion connector section which is used to connect an expansion board, in which the housing projection section includes an inclined section downwardly inclined from the one end side toward an other end side in the longitudinal direction, and the expansion connector section is provided in the inclined section.

Abstract: An electronic device includes: a first case provided with an opening portion; a second case that has one end portion provided with a fulcrum portion engaged with the first case and rotates about the fulcrum portion to close the opening portion in an openable manner, and a packing portion that is provided to be inclined to be more on an inner side of the second case at a portion closer to the fulcrum portion of the second case, and comes into pressure contact with an edge portion of the opening portion when the second case closes the opening portion.

Abstract: An electronic device includes: a first case provided with an opening portion; a second case that has one end portion provided with a fulcrum portion engaged with the first case and rotates about the fulcrum portion to close the opening portion in an openable manner, and a packing portion that is provided to be inclined to be more on an inner side of the second case at a portion closer to the fulcrum portion of the second case, and comes into pressure contact with an edge portion of the opening portion when the second case closes the opening portion.

Abstract: A mobile device of the present invention having an upper case, a lower case arranged under the upper case, and a middle case arranged inside the upper case and the lower case, includes a first engaging section which is provided in the peripheral edge portion of the undersurface of the upper case, a second engaging section which is provided in the peripheral edge portion of the top surface of the middle case and engages with the first engaging section, a third engaging section which is provided in the peripheral edge portion of the undersurface of the middle case, and a fourth engaging section which is provided in the peripheral edge portion of the top surface of the lower case and engages with the third engaging section.

Abstract: A mobile device of the present invention includes a cover member which covers the opening section of a storage section provided in the device case. The cover member includes an outer cover section which forms a portion of the outer shape of the device case, and an inner cover section which is attached to the inner side of the outer cover section and detachably inserted into the opening section of the storage section. In addition, a gasket groove which is open in two directions perpendicular to each other toward the outer cover section side and the outer peripheral side of the inner cover section is provided in the outer peripheral portion of the inner cover section along the outer periphery of the inner cover section, so as to be located closer to the center side than the outer periphery of the outer cover section.

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

Abstract: As and B are implanted to side surfaces of trenches 3 by a rotation ion implanting method, and by using a difference between these impurities in diffusion coefficient, the structure in which an n?-type epitaxial Si layer is interposed between trenches 3 is converted into a semiconductor structure consisting of n-type pillar layer 5/p-type pillar layer 4/n-type pillar layer 5 lining up. The structure can function substantially the same role as that of a super junction structure.

Abstract: In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the photo receiving element configured to receive the optical signal and generate an electrical signal; and a control circuit having an active element, a source and a drain of the active element connected to both ends of the photo receiving element; wherein the breakdown voltage of the control circuit is no more than an open circuit voltage of the photo receiving element.

Abstract: In various aspects, a MOSFET may include a semiconductor region of a first conductivity type; a first semiconductor region of a second conductivity type provided in the semiconductor region; a second semiconductor region of the first conductivity type provided in the semiconductor region, the second semiconductor region having a higher impurity concentration than the semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region; a fourth semiconductor region of the second conductivity type configured to be contact with the first semiconductor region and the third semiconductor region, the fourth semiconductor region having a lower impurity concentration than the first semiconductor region and the third semiconductor region; a gate electrode provided on the fourth semiconductor region via a gate insulating layer, an edge of the gate electrode spaced from a junction between the first semiconductor region and the fourth semiconductor region.

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a vertical unit cell and a separating member. The unit cell includes a second conductivity type semiconductor layer and two first conductivity type semiconductor layers to interpose the second conductivity type semiconductor layer from both side surfaces. A pn junction boundary between the second and first conductivity type semiconductor layer is substantially vertical to the main surface of the semiconductor substrate. A second conductivity type base layer on an upper surface of the second conductivity type semiconductor layer has an impurity concentration higher than the second conductivity type semiconductor layer. A first conductivity type source diffusion layer is on a surface of the base layer. A gate insulating film is formed on the base layer interposed between the source diffusion layer and the first conductivity type semiconductor layer. A gate electrode is formed on the gate insulating film.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type juxtaposed on a semiconductor substrate of the first conductivity type. The first semiconductor layer has an impurity concentration lower than that of the semiconductor substrate. The second semiconductor layer has at a central location a trench, which extends from the upper end toward the semiconductor substrate. A first region of the second conductivity type is formed to include an upper portion of the second semiconductor layer. A second region of the first conductivity type is formed in a surface of the first region. A gate electrode is disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the first semiconductor layer.

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: A P type source region is formed in a grid mesh-like pattern in one major surface portion of an N.sup.- type semiconductor substrate. A P type base region and P.sup.- type base region are each formed in the one major surface portion of the N.sup.- type semiconductor substrate at an area between those grid mesh-like portions of the P type source region. An N type emitter region is formed in the P type base region. An N type emitter region is formed in the P.sup.- type base region. A gate electrode is formed over the P type source region, N.sup.- type semiconductor substrate, P type base region and P.sup.- type base region. The gate electrode is formed in a grid mesh-like pattern as viewed from above the N.sup.- type semiconductor substrate. A cathode electrode is contacted with the P type source region, P.sup.- type base region and N type emitter regions. A P.sup.+ type emitter layer is formed on an other major surface side of the N.sup.- type semiconductor substrate. An N.sup.

Abstract: Disclosed is a semiconductor device comprising an output Triode AC switch with a vertical structure, which is provided in a silicon substrate and has a gate, a first output terminal and a second output terminal, and an input/driving photo Triode AC switch, which is provided in the substrate and has a light-receiving portion, a first terminal connected to the gate and a second terminal connected to the second output terminal. The output Triode AC switch with a vertical structure is turned on when light is input to the photo Triode AC switch.