Patents by Inventor Yasuo Amano
Yasuo Amano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8453077Abstract: A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease.Type: GrantFiled: July 17, 2012Date of Patent: May 28, 2013Assignee: Fujitsu LimitedInventors: Sumiko Makino, Yasuo Amano
-
Publication number: 20130070206Abstract: In a laser source module aligning laser beams from laser sources for three colors, red, green, and blue on a single combined beam optical axis, decreasing relative displacements of beam spots of three colors, occurring due to thermal deformation by temperature rise, is achieved by a laser source module including plural laser sources, each incorporating a laser having a laser chip installed on a heat sink and a lens converting a light radiated from the laser into a laser beam, and a beam combining unit aligning the laser beams from the laser sources on a single combined beam optical axis, wherein the lasers in at least two or more ones of the laser sources are arranged so that their laser beams will be decentered toward a same direction on the combined beam optical axis upon displacement of an emission point of the laser chip away from the heat sink.Type: ApplicationFiled: March 26, 2012Publication date: March 21, 2013Applicant: HITACHI MEDIA ELECTRONICS CO., LTD.Inventors: Atsushi KAZAMA, Takeshi NAKAO, Yasuo AMANO
-
Publication number: 20120284681Abstract: A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: FUJITSU LIMITEDInventors: Sumiko MAKINO, Yasuo AMANO
-
Patent number: 8249849Abstract: An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.Type: GrantFiled: January 22, 2009Date of Patent: August 21, 2012Assignee: Fujitsu LimitedInventor: Yasuo Amano
-
Patent number: 8110907Abstract: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced.Type: GrantFiled: January 8, 2009Date of Patent: February 7, 2012Assignee: Elpida Memory, Inc.Inventors: Masahiro Yamaguchi, Emi Sawayama, Hiroshi Oyama, Shigeharu Tsunoda, Yasuo Amano, Naoki Matsushima
-
Publication number: 20120010061Abstract: A paper discharge apparatus includes a conveying path configured to convey a paper from an upstream portion to a downstream portion. A preventing mechanism is provided on the conveying path. The preventing mechanism is configured to prevent the paper from being conveyed to the downstream portion by pushing the paper or blocking the conveying path. A control unit is configured to bend the paper by preventing the conveyance of the paper by using the preventing mechanism, and then convey the paper to the downstream portion of the conveying path for discharge of the paper from the conveying path.Type: ApplicationFiled: February 24, 2011Publication date: January 12, 2012Applicant: TOSHIBA TEC KABUSHIKI KAISHAInventors: Toshiharu Sekino, Yasuo Amano
-
Publication number: 20110313709Abstract: A power circuit analysis apparatus includes a segmentation unit that segments an analysis target region in a power circuit included in an analysis target circuit into a plurality of segmented regions, and an analysis unit that outputs an analysis result of the power circuit with respect to each of the plurality of segmented regions on a basis of a consumption current value in the segmented region and a number of via holes formed in each interlayer connecting power line wirings in upper and lower layers to each other in the segmented region.Type: ApplicationFiled: June 10, 2011Publication date: December 22, 2011Applicant: FUJITSU LIMITEDInventors: Miki TERABE, Yasuo Amano
-
Publication number: 20090299718Abstract: An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.Type: ApplicationFiled: January 22, 2009Publication date: December 3, 2009Applicant: Fujitsu LimitedInventor: Yasuo Amano
-
Publication number: 20090206492Abstract: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced.Type: ApplicationFiled: January 8, 2009Publication date: August 20, 2009Applicant: Elpida Memory, Inc.Inventors: Masahiro Yamaguchi, Emi Sawayama, Hiroshi Oyama, Shigeharu Tsunoda, Yasuo Amano, Naoki Matsushima
-
Patent number: 7569967Abstract: A disk device has a small size, a small thickness, a high efficiency, a small degree of vibration and a small level of noise. In one embodiment, the disk device comprises a disk for storing information and a disk drive for driving the disk. The disk drive includes a rotor portion mounting an annular permanent magnet on the outer peripheral portion thereof, and a stator portion disposed on the outer side in the radial direction of the annular permanent magnet. The stator portion is constituted by a wiring board provided with a stator core formed by laminating magnetic metal plates in a radial manner and a coil that is so formed as to surround the stator core while electrically connecting wiring layers and through hole portions. The coil is so formed that among the envelopes connecting the outermost peripheral surfaces of the coil in the radial direction, the neighboring envelops and intersect at an inner position in the radial direction.Type: GrantFiled: June 19, 2006Date of Patent: August 4, 2009Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yuji Fujita, Yasuo Amano, Yoshihide Yamaguchi
-
Publication number: 20080185729Abstract: A semiconductor device is provided with a film substrate that has through-vias that are formed by filling a conductive material in through-holes that pass through the front and rear of a film-shaped substrate body and wiring or terminals that connect to the through-vias, with a semiconductor element being mounted on the film-shaped substrate body by terminal members thereof being electrically connected to the wiring or terminals of the film substrate.Type: ApplicationFiled: January 30, 2008Publication date: August 7, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Masahiro Yamaguchi, Naoya Kanda, Yasuo Amano, Shigeharu Tsunoda
-
Publication number: 20080037405Abstract: The present invention achieves a disc recording and reproducing apparatus capable of using an inexpensive disc by loosening the tolerance of track offset of each layer of a multilayer optical disc, and capable of ensuring the reliability of the disc by relieving external forces exerted on the disc at the loading or unloading of the disc. A disc holder that rotates while holding a multilayer optical disc is configured of a non-moving part fixed to a rotating shaft, and a moving part. Actuators are used to drive the moving part having the optical disc fixed thereto relative to the non-moving part, thereby correcting the offset of a recording layer with respect to the rotating shaft.Type: ApplicationFiled: May 21, 2007Publication date: February 14, 2008Inventors: Yuji Fujita, Naoko Fujita, Shohei Fujita, Naoko Fujita, Yasuo Amano, Hiroyuki Minemura, Akemi Hirotsune
-
Publication number: 20070121428Abstract: A multilayer optical recording apparatus excellent in high-speed recording and long-term reliability is realized, the apparatus preventing the lowering of a speed of switching recording layers by preventing an increase in contact resistance attributable to wear of a rolling part or of a sliding part of the apparatus. In a multilayer optical recording apparatus using an electrochromic material, a rotary transformer is provided as electromagnetic induction means for supplying power from a power source to a medium.Type: ApplicationFiled: November 28, 2006Publication date: May 31, 2007Inventors: Yuji Fujita, Yasuo Amano, Akemi Hirotsune
-
Patent number: 7191421Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.Type: GrantFiled: March 25, 2002Date of Patent: March 13, 2007Assignee: Fujitsu LimitedInventors: Yasuo Amano, Hiroshi Seki, Yukio Makino, Yumiko Yamanishi, Yoshiko Nakanishi, Yoichiro Ishikawa
-
Publication number: 20060290228Abstract: A disk device has a small size, a small thickness, a high efficiency, a small degree of vibration and a small level of noise. In one embodiment, the disk device comprises a disk for storing information and a disk drive for driving the disk. The disk drive includes a rotor portion mounting an annular permanent magnet on the outer peripheral portion thereof, and a stator portion disposed on the outer side in the radial direction of the annular permanent magnet. The stator portion is constituted by a wiring board provided with a stator core formed by laminating magnetic metal plates in a radial manner and a coil that is so formed as to surround the stator core while electrically connecting wiring layers and through hole portions. The coil is so formed that among the envelopes connecting the outermost peripheral surfaces of the coil in the radial direction, the neighboring envelops and intersect at an inner position in the radial direction.Type: ApplicationFiled: June 19, 2006Publication date: December 28, 2006Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yuji Fujita, Yasuo Amano, Yoshihide Yamaguchi
-
Patent number: 7035044Abstract: A magnetic disk drive includes a base constituting at least a face included in an enclosure; a shaft secured to the base; a rotor which rotates around the shaft as a rotary axis; a stator for rotating the rotor; and a magnetic disk secured to the rotor; wherein the stator is disposed on a face facing the base. This improves durability of the magnetic disk drive.Type: GrantFiled: June 10, 2002Date of Patent: April 25, 2006Assignee: Hitachi Global Storage Technologies Japan, Ltd.Inventors: Asao Nakano, Yuji Fujita, Yasuo Amano, Nobuyuki Ushifusa, Koki Uefuna, Takashi Yamaguchi, Toshiyuki Ajima
-
Patent number: 7035055Abstract: A magnetic disk apparatus includes a magnetic disk on which information is stored, a magnetic head which performs writing-in and reading-out of information, a suspension which supports the magnetic head, and a suspension supporting member having a ?-shaped hinge. The suspension is supported at a tip end of the ?-shaped hinge and an actuator for moving the magnetic head to a predetermined position on the magnetic disk is disposed so as to bridge an open portion of the ?-shaped hinge. The actuator is coated with a resin material.Type: GrantFiled: September 5, 2003Date of Patent: April 25, 2006Assignee: Hitachi Global Storage Technologies Japan, Ltd.Inventors: Haruhiko Kikkawa, Yasuo Amano, Shigeo Nakamura, Osamu Narisawa
-
Patent number: 6950276Abstract: A disk drive comprising a rotor, to which a disk and a plurality of magnets are fixed, and an open-slot type integrally molded stator disposed about an outer periphery of the magnets, and wherein the stator comprises coils formed by etching metallic films on teeth. The invention may also be applied to a closed-slot type stator. With either type, it is possible to produce an opening that is equal to or smaller than the thickness of a coil wire and cogging torque is minimized.Type: GrantFiled: August 22, 2002Date of Patent: September 27, 2005Assignee: Hitachi, Ltd.Inventors: Yuji Fujita, Asao Nakano, Yasuo Amano, Nobuyuki Ushifusa, Kouki Uefune, Takashi Yamaguchi, Toshiyuki Ajima
-
Patent number: 6943984Abstract: An object of the invention is to inhibit a turning force of a magnetic disc apparatus from being reduced. In order to achieve the object, there is provided a magnetic disc apparatus having a rotor to which a magnetic disc fixed, and a stator which is filled with a resin between stator coils, wherein a member having a lower expansion coefficient than a thermal expansion coefficient of the resin is arranged between the stator coils.Type: GrantFiled: August 16, 2002Date of Patent: September 13, 2005Assignee: Hitachi, Ltd.Inventors: Yasuo Amano, Asao Nakano, Yuji Fujita, Nobuyuki Ushifusa, Kouki Uefune, Takashi Yamaguchi, Toshiyuki Ajima
-
Patent number: 6781783Abstract: Provided is a magnetic disc apparatus comprising a magnetic head for writing and reading data to and from a magnetic disc, a slider for floating up the magnetic head from the magnetic disc on rotation, a suspension having an IC chip mounting surface, for supporting the slider, a positioning mechanism for positioning a magnetic head at a predetermined position, and an IC chip mounted on the IC chip supporting surface of the suspension, wherein the rate of variation in temperature difference between opposite sides of the IC chip mounting position as a center on the IC chip mounting surface is set to be below about 3.5 K/sec. Thereby it is possible to restrain the averaged seek time for the magnetic disc from becoming longer.Type: GrantFiled: December 18, 2001Date of Patent: August 24, 2004Assignee: Hitachi, Ltd.Inventors: Yasuo Amano, Shigeo Nakamura, Osamu Narisawa, Mikio Tokuyama, Masahito Kobayashi, Hiroyasu Sasaki, Yuuji Fujita