Patents by Inventor Yasuo Arai

Yasuo Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145937
    Abstract: A radio wave control system includes a phase adjustment plate that transmits a radio wave from a second main surface to a first main surface and focuses the radio wave on a focal point; and a reflection plate installed at a position irradiated with the radio wave transmitted through the phase adjustment plate.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Applicant: AGC Inc.
    Inventors: Akira KUMAGAI, Keisuke ARAI, Osamu KAGAYA, Yasuo MORIMOTO
  • Patent number: 11949160
    Abstract: A distributed antenna includes a strip member extending in a strip-like shape including a dielectric body of a plate shape having a first surface that is one surface of the dielectric body and a second surface that is opposite to the first surface; a transmission line provided on the first surface, on the second surface, or between the first surface and the second surface; and a plurality of antenna elements electrically connected to the transmission line and disposed in a distributed manner on the first surface or on the second surface, or electrically connected to the transmission line and disposed in a distributed manner between the first surface and the second surface.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 2, 2024
    Assignee: AGC Inc.
    Inventors: Akira Kumagai, Yasuo Morimoto, Takeshi Motegi, Keisuke Arai, Osamu Kagaya
  • Patent number: 11795413
    Abstract: The invention relates to a poly alkyl(meth)acrylate polymer comprising polybutadiene-based monomer units and a process for preparing the same. The invention also relates to the use of said polymer as a viscosity index improver in lubricant formulation and to lubricant compositions comprising said polymer.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Evonik Operations GmbH
    Inventors: Tsuyoshi Yuki, Tomohiro Matsuda, Yasuo Arai
  • Patent number: 11639481
    Abstract: An additive composition contains a viscosity index improver and a pour point depressant. A process can be used for preparing the additive composition. The additive composition can be used as a lubricant additive in a lubricating oil formulation, and lubricating oil formulations can contain the additive composition.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: May 2, 2023
    Assignee: Evonik Operations GmbH
    Inventors: Tsuyoshi Yuki, Yasuo Arai, Tomohiro Matsuda, Nobuhiro Kishida
  • Publication number: 20230025387
    Abstract: An additive composition contains a viscosity index improver and a pour point depressant. A process can be used for preparing the additive composition. The additive composition can be used as a lubricant additive in a lubricating oil formulation, and lubricating oil formulations can contain the additive composition.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 26, 2023
    Applicant: Evonik Operations GmbH
    Inventors: Tsuyoshi YUKI, Yasuo Arai, Tomohiro Matsuda, Nobuhiro Kishida
  • Publication number: 20220306962
    Abstract: The invention relates to a poly alkyl(meth)acrylate polymer comprising polybutadiene-based monomer units and a process for preparing the same. The invention also relates to the use of said polymer as a viscosity index improver in lubricant formulation and to lubricant compositions comprising said polymer.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 29, 2022
    Applicant: Evonik Operations GmbH
    Inventors: Tsuyoshi Yuki, Tomohiro Matsuda, Yasuo Arai
  • Patent number: 10941368
    Abstract: Selected comb polymers contain specified amounts of macromonomer and nitrogen-containing (meth)acrylates. Lubricant compositions can contain such comb polymers. The selected comb polymers can be used as solubilizers in lubricant compositions, especially in engine oil (EO) compositions.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 9, 2021
    Assignee: Evonik Operations GmbH
    Inventors: Tsuyoshi Yuki, Yasuo Arai, Tomohiro Matsuda, Nobuhiro Kishida
  • Patent number: 10622263
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 14, 2020
    Assignees: LAPIS SEMICONDUCTOR CO., LTD., Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Publication number: 20190367836
    Abstract: Selected comb polymers contain specified amounts of macromonomer and nitrogen-containing (meth)acrylates. Lubricant compositions can contain such comb polymers. The selected comb polymers can be used as solubilizers in lubricant compositions, especially in engine oil (EO) compositions.
    Type: Application
    Filed: December 15, 2017
    Publication date: December 5, 2019
    Applicant: Evonik Oil Additives GmbH
    Inventors: Tsuyoshi YUKI, Yasuo Arai, Tomohiro Matsuda, Nobuhiro Kishida
  • Patent number: 10418985
    Abstract: The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: September 17, 2019
    Assignees: INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION, HIGH ENERGY ACCELERATION RESEARCH ORGANIZATION
    Inventors: Ikuo Kurachi, Yasuo Arai, Miho Yamada
  • Publication number: 20190131965
    Abstract: The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 2, 2019
    Applicant: Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Ikuo Kurachi, Yasuo Arai, Miho Yamada
  • Publication number: 20180138232
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Applicants: LAPIS Semiconductor Co., Ltd., Inter-University Research Institute Corporation High Energy Accelerator Research Organization
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 9899448
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 20, 2018
    Assignees: LAPIS Semiconductor Co., Ltd., INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 9878708
    Abstract: A drive system includes a drive source and a transmission mechanism transmitting a torque between the drive source and a drive wheel. The transmission mechanism includes at least one clutch switching between an engaged state of transmitting the torque between elements constituting the drive system and a disengaged state of failing to transmit the torque. An ECU detects at least one loaded state in which an excessively large torque can be applied to the drive system in a direction from the drive wheel, and disengages a predetermined clutch when the at least one loaded state in which an excessively large torque can be applied is detected. In the case where an excessively large torque can be applied to the drive system, the torque applied to a predetermined element constituting the drive system can be blocked and the torque applied to the drive system can be suppressed with a good response.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: January 30, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yasuo Arai
  • Publication number: 20160236676
    Abstract: A drive system includes a drive source and a transmission mechanism transmitting a torque between the drive source and a drive wheel. The transmission mechanism includes at least one clutch switching between an engaged state of transmitting the torque between elements constituting the drive system and a disengaged state of failing to transmit the torque. An ECU detects at least one loaded state in which an excessively large torque can be applied to the drive system in a direction from the drive wheel, and disengages a predetermined clutch when the at least one loaded state in which an excessively large torque can be applied is detected. In the case where an excessively large torque can be applied to the drive system, the torque applied to a predetermined element constituting the drive system can be blocked and the torque applied to the drive system can be suppressed with a good response.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 18, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yasuo ARAI
  • Publication number: 20160190203
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 9318391
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 19, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Publication number: 20150126002
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: Yasuo ARAI, Masao OKIHARA, Hiroki KASAI
  • Patent number: 8963246
    Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: February 24, 2015
    Assignees: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd.
    Inventors: Yasuo Arai, Masao Okihara, Hiroki Kasai
  • Patent number: 8928101
    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: January 6, 2015
    Assignees: LAPIS Semiconductor Co., Ltd., RIKEN
    Inventors: Hiroki Kasai, Yasuo Arai, Takaki Hatsui