Abstract: An IGBT region (2) and a diode region (3) are provided on a semiconductor substrate (1) and have an emitter electrode (16) on a surface of the semiconductor substrate (1). A sense IGBT region (4) is provided on the semiconductor substrate (1), has a smaller area than that of the IGBT region (2), and includes a sense emitter electrode (20) provided on the surface of the semiconductor substrate (1) and separated from the emitter electrode (16). A sense diode region (3) is provided on the semiconductor substrate (1), has a smaller area than that of the diode region (3), and includes a sense anode electrode provided on the surface of the semiconductor substrate (1) and separated from the emitter electrode (16). The sense diode region (3) is separated from the IGBT region (2) by a distance equal to or greater than that of the drift layer (8).

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having impurity concentration lower than impurity concentration of the first semiconductor layer, a well region provided on an upper surface side of the second semiconductor layer in the active region, a source region provided on an upper surface side of the well region, a high concentration region provided on the upper surface side of the second semiconductor layer in the termination region and having impurity concentration higher than impurity concentration of the well region, a gate electrode provided immediately above the well region and a source electrode electrically connected to the source region and the high concentration region, wherein the first semiconductor layer has an impurity concentration of equal to or greater than 4×1018 cm?3 and has a thickness of equal to or greater than 4 ?m.

Abstract: A semiconductor device includes: a semiconductor substrate; an upper surface electrode formed on an upper surface side of the semiconductor substrate; an insulating film formed on the upper surface side of the semiconductor substrate; and a lower surface electrode formed on a lower surface side of the semiconductor substrate and having a larger area than that of the upper surface electrode, wherein the upper surface electrode and the lower surface electrode are electrodes having a compressive stress.

Abstract: A Schottky barrier diode according to the present disclosure includes an n-type semiconductor substrate, one or more p-type guard rings provided on a side of an upper surface of the semiconductor substrate, an anode electrode provided on the upper surface of the semiconductor substrate, a cathode electrode provided on a rear surface of the semiconductor substrate and an insulating film provided on an inner guard ring on an innermost side among the one or more guard rings, wherein the anode electrode rides on the insulating film and has its end portion provided just above the inner guard ring, the anode electrode and the inner guard ring are provided away from each other, and a thickness of the insulating film is 1.0 ?m or more.

Abstract: A semiconductor device includes a semiconductor substrate, an effective region formed as a conductive section on the semiconductor substrate, an ineffective region formed as a non-conductive section on the semiconductor substrate, a wiring metal formed in the effective region, a metal section provided on an upper surface of the wiring metal and exposed to an outside, an identifying mark provided on the upper surface of the wiring metal and exposed to the outside, the identifying mark being spaced apart from the metal section, and an insulating body provided on the upper surface of the wiring metal and exposed to the outside, the insulating body being adjacent to the metal section and the identifying mark.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

Abstract: A semiconductor device includes an effective region being a region where a semiconductor element is formed, a chip end portion being an outer peripheral portion of a semiconductor layer, and a withstand voltage holding region disposed between the effective region and the chip end portion. The top of the withstand voltage holding region is covered by a protective film (15) including a first layer (15a) and a second layer (15b) formed on the first layer (15a). The first layer (15a) and the second layer (15b) of the protective film (15) have the same composition. The second layer (15b) is an uppermost layer of the protective film (15) and is formed such that an upper surface of the protective film (15) has a shape having raised portions and recessed portions.

Abstract: A semiconductor device includes, on an upper surface side of an N?-type drift layer, a P-type well layer, an N-type emitter layer, a gate insulation film, and a gate electrode, and includes, on a lower surface side of the N?-type drift layer, an N-type buffer layer, a P-type collector layer, and an N++-type layer. The N++-type layer is partially formed in the N-type buffer layer. The N++-type layer has impurity concentration being higher than impurity concentration of the N-type buffer layer and being equal to or higher than impurity concentration of the P-type collector layer.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

Abstract: A back surface of a wafer is formed with a ring-shaped projecting portion. The wafer is cut with a blade from a side of a front surface of the wafer in a state where the projecting portion of the wafer with a back surface facing upward is supported.

Abstract: A semiconductor device includes, on an upper surface side of an N?-type drift layer, a P-type well layer, an N-type emitter layer, a gate insulation film, and a gate electrode, and includes, on a lower surface side of the N?-type drift layer, an N-type buffer layer, a P-type collector layer, and an N++-type layer. The N++-type layer is partially formed in the N-type buffer layer. The N++-type layer has impurity concentration being higher than impurity concentration of the N-type buffer layer and being equal to or higher than impurity concentration of the P-type collector layer.

Abstract: A semiconductor device includes a semiconductor substrate, an effective region formed as a conductive section on the semiconductor substrate, an ineffective region formed as a non-conductive section on the semiconductor substrate, a wiring metal formed in the effective region, a metal section provided on an upper surface of the wiring metal and exposed to an outside, an identifying mark provided on the upper surface of the wiring metal and exposed to the outside, the identifying mark being spaced apart from the metal section, and an insulating body provided on the upper surface of the wiring metal and exposed to the outside, the insulating body being adjacent to the metal section and the identifying mark.

Abstract: A back surface of a wafer is formed with a ring-shaped projecting portion. The wafer is cut with a blade from a side of a front surface of the wafer in a state where the projecting portion of the wafer with a back surface facing upward is supported.

Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).

Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).

Abstract: A main cell and a sense cell are formed in a first and second region of a semiconductor substrate respectively. A base layer is formed on a drift layer in the first and second regions. A first conductivity type impurity is implanted in the base layer by using a mask having first and second openings respectively on the first and second regions in order to form first and second emitter regions on the base layer respectively in the first and second regions. First and second contact regions, first and second trench gates, and a collector layer are formed. An area of the second opening is smaller than an area of the first opening. Threshold voltage of the sense cell is higher than threshold voltage of the main cell.

Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.