Patents by Inventor Yasuo Ebuchi

Yasuo Ebuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7321183
    Abstract: A film bulk acoustic resonator, includes first to fourth insulator patterns disposed apart from each other. The third and fourth insulator patterns are disposed opposite the second and first insulator patterns in relation to the first and second insulating patterns, respectively. A bottom conductive layer is disposed above the first and third insulator patterns spreading from a region between the first and second insulator patterns to the third insulator pattern. A piezoelectric film is provided on the bottom conductive layer, disposed above the region between the first and second insulating patterns. A top conductive layer is facing the bottom conductive layer so as to sandwich the piezoelectric film, spreading from the region between the first and second insulator patterns to the fourth insulator pattern.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: January 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ebuchi, Takako Motai, Kenya Sano
  • Patent number: 7236066
    Abstract: A film bulk acoustic resonator includes a first electrode, a piezoelectric film disposed on the first electrode, a second electrode disposed on the piezoelectric film or disposed above the piezoelectric film, and an additional film disposed on and abutting the piezoelectric film. The additional film has at least one pair of opposite sides which are non-parallel with each other. The additional film includes a plurality of stripe-shaped openings.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Ebuchi
  • Patent number: 7176521
    Abstract: A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and co
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiko Kawamura, Noboru Matsuda, Yasuo Ebuchi
  • Publication number: 20060255883
    Abstract: A film bulk acoustic resonator includes a first electrode; a piezoelectric film disposed on the first electrode; a second electrode disposed on the piezoelectric film or disposed above the piezoelectric film; and an additional film disposed on and abutting the piezoelectric film, the additional film having at least one pair of opposite sides which are non-parallel with each other.
    Type: Application
    Filed: August 5, 2005
    Publication date: November 16, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuo Ebuchi
  • Patent number: 7045858
    Abstract: There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Matsuda, Shoji Takayama, Yasuo Ebuchi
  • Publication number: 20050199953
    Abstract: A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and co
    Type: Application
    Filed: April 30, 2004
    Publication date: September 15, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiko Kawamura, Noboru Matsuda, Yasuo Ebuchi
  • Publication number: 20050191810
    Abstract: There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.
    Type: Application
    Filed: April 9, 2004
    Publication date: September 1, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Matsuda, Shoji Takayama, Yasuo Ebuchi
  • Publication number: 20050142888
    Abstract: A film bulk acoustic resonator, includes first to fourth insulator patterns disposed apart from each other. The third and fourth insulator patterns are disposed opposite the second and first insulator patterns in relation to the first and second insulating patterns, respectively. A bottom conductive layer is disposed above the first and third insulator patterns spreading from a region between the first and second insulator patterns to the third insulator pattern. A piezoelectric film is provided on the bottom conductive layer, disposed above the region between the first and second insulating patterns. A top conductive layer is facing the bottom conductive layer so as to sandwich the piezoelectric film, spreading from the region between the first and second insulator patterns to the fourth insulator pattern.
    Type: Application
    Filed: July 15, 2004
    Publication date: June 30, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuo Ebuchi, Takako Motai, Kenya Sanoi