Patents by Inventor Yasuo Gotoh

Yasuo Gotoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220243035
    Abstract: Provided is a cellulose solution (a composition) in which decomposition of cellulose does not easily proceed even if heated. Further, provided is a method for producing a cellulose fiber excellent in mechanical strength. The composition includes cellulose and a compound represented by the following formula (1), a concentration of 1-methylimidazolium chloride being 300 ppm or less on a mass basis with respect to the compound represented by the formula (1). In the formula (1), R is an alkyl group having 2 to 6 carbon atoms, and Me is a methyl group.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 4, 2022
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Kimihiro AOYAMA, Tetsuhiko MIZUSAKA, Yasuyoshi NAKAYASU, Yasuo GOTOH
  • Patent number: 7359262
    Abstract: A semiconductor memory device according to the present invention where the entire memory area determined by an array of memory cells is divided into a plurality of memory areas comprises at least one relief memory area for redundancy relieving a fault memory area which contains a fault memory cell, a fault address storing means in which a fault address is stored, a comparator circuit for comparing an address of the memory area specified by an input address with the fault address and when the input address corresponds to the fault address, selecting the corresponding relief memory area, wherein the comparator circuit selects the corresponding relief memory area upon receiving from the outside a relief memory area select signal indicative of selection of the relief memory area even when the address of the memory area specified by the address input does not correspond to the fault address.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: April 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yasuo Gotoh
  • Publication number: 20060262615
    Abstract: A semiconductor memory device according to the present invention where the entire memory area determined by an array of memory cells is divided into a plurality of memory areas comprises at least one relief memory area for redundancy relieving a fault memory area which contains a fault memory cell, a fault address storing means in which a fault address is stored, a comparator circuit for comparing an address of the memory area specified by an input address with the fault address and when the input address corresponds to the fault address, selecting the corresponding relief memory area, wherein the comparator circuit selects the corresponding relief memory area upon receiving from the outside a relief memory area select signal indicative of selection of the relief memory area even when the address of the memory area specified by the address input does not correspond to the fault address.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 23, 2006
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Yasuo Gotoh