Abstract: An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error; and a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.

Abstract: An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error; and a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.

Abstract: An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

Abstract: An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.

Abstract: An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

Abstract: A method of computing includes defining a first atomic random variable (ARV) and first random variable (RV) in a programming language system. The first ARV having a non-deterministic value of either zero according to a second probability or one according to a first probability. A sum of the first probability and the second probability is one. A covariance of the first ARV and a second ARV is zero. The first RV has a first indefinite value at a first definite probability and includes a polynomial of one or more atomic random variables (ARVS) that includes the first ARV. The method includes executing a computer instruction that includes a mathematical operation involving the first RV as a basic data type and produces a second RV having a second indefinite value at a second definite probability, represents a result distribution, and tracks a response to the one or more ARVS.

Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

Abstract: A method of computing includes defining a first atomic random variable (ARV) and first random variable (RV) in a programming language system. The first ARV having a non-deterministic value of either zero according to a second probability or one according to a first probability. A sum of the first probability and the second probability is one. A covariance of the first ARV and a second ARV is zero. The first RV has a first indefinite value at a first definite probability and includes a polynomial of one or more atomic random variables (ARVS) that includes the first ARV. The method includes executing a computer instruction that includes a mathematical operation involving the first RV as a basic data type and produces a second RV having a second indefinite value at a second definite probability, represents a result distribution, and tracks a response to the one or more ARVS.

Abstract: A device for converting frequency-domain data to time-domain data may be provided. The device may include one or more processors. The one or more processors may be configured to transform frequency-domain data to a complex conjugate symmetric of the frequency-domain data over an entire range of frequencies while maintaining a maximum frequency. The one or more processors may further be configured to apply an Inverse Discrete Fourier Transform operation to the complex conjugate symmetric of the frequency-domain data to generate time-domain data.

Abstract: A method of adaptive control is provided. The method may include measuring a first set of average sign values of inter-symbol interference (ISI) of an output signal with a set of control parameters using correlation. The method may further include determining a first set of Q values. The method may also include adjusting the set of control parameters based on the first set of Q values. The method may include measuring a second set of average sign values of ISI using inverted correlation. The method may further include determining a second set of Q values. The method may also include determining a difference between the first set of Q values and the second set of Q values. The method may further include adjusting the set of control parameters based on the difference between the first set of Q values and the second set of Q values. The method may further include adjusting the output signal based on the set of control parameters.

Abstract: A decision feedback equalizer may include an input node, first and second paths, and a summation circuit. The input node may be configured to receive an input signal with an input symbol rate. The first and second paths may receive the input signal. The first path may include a first register configured to output a first signal based on the input signal such that the first signal has a sample symbol rate less than the input symbol rate. The second path may include a second register configured to output a second signal at the sample symbol rate based on the input signal. The summation circuit may be positioned between the input node and the first and second paths. The summation circuit may subtract the first and seconds signals at the sample symbol rate from the input signal before the input signal is provided to the first and second paths.

Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

Abstract: A method of selecting filter patterns is provided. The method may include measuring an average sign value of aggregate inter-symbol interference (ISI) for a data sequence using multiple filter pattern combinations of multiple filter patterns; estimating a first analog level of aggregate ISI for a first filter pattern based on a first average sign value, and a second analog level of aggregate ISI for a second filter pattern based on a second average sign value; estimating an analog level of individual ISI of the first filter pattern pair based on the first analog level and the second analog level; estimating, for each possible filter pattern combination, an analog level of aggregate ISI for the first filter pattern pair; and selecting a filter pattern combination for the first filter pattern pair that reduces the analog level of aggregate ISI.

Abstract: A method of selecting filter patterns is provided. The method may include measuring an average sign value of aggregate inter-symbol interference (ISI) for a data sequence using multiple filter pattern combinations of multiple filter patterns; estimating a first analog level of aggregate ISI for a first filter pattern based on a first average sign value, and a second analog level of aggregate ISI for a second filter pattern based on a second average sign value; estimating an analog level of individual ISI of the first filter pattern pair based on the first analog level and the second analog level; estimating, for each possible filter pattern combination, an analog level of aggregate ISI for the first filter pattern pair; and selecting a filter pattern combination for the first filter pattern pair that reduces the analog level of aggregate ISI.

Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

Abstract: A differential signal transmission line may include first, second, and third conductors and first and second insulative materials. The first and second conductors may be configured to carry positive and negative signals of a differential signal. The first insulative material may be positioned between the first conductor and the second conductor and may have an effect on a differential mode dielectric constant of the differential signal that is greater than an effect on a common mode dielectric constant of the differential signal. The second insulative material may be positioned to electrically isolate the third conductor from the first conductor, the second conductor, and the first insulative material and may have an effect on the differential mode dielectric constant of the differential signal that is lower than an effect on the common mode dielectric constant of the differential signal.

Abstract: A circuit board may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The circuit board may also include a first dielectric material disposed between the first trace and the second trace. The first dielectric material may include a first weave pattern and the first trace and the second trace may be rotated with respect to a first orientation of the first weave pattern. Further, the circuit board may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric value of the first dielectric material and a second dielectric value of the second dielectric material may suppress a mode conversion of a differential signal.

Abstract: A circuit may include a signal path, a first layer including the signal path, and a second layer including the signal path. The circuit may additionally include a path via having a signal-path via location and configured to connect the signal path at the first layer with the signal path at the second layer. The circuit may also include a ground plane associated with the first layer. The ground plane may have a ground-plane location that corresponds to the signal-path via location. The ground plane may also include an asymmetrical cutout portion that extends away from the ground-plane location on a first side of the ground plane that is opposite a second side of the ground plane that corresponds with a side of the first layer where the path via interfaces with the signal path at the first layer.

Abstract: A circuit may include a differential via that may include a first via having a first-via length and a second via having a second-via length longer than the first-via length. The circuit may also include a differential stripline coupled to the differential via. The differential stripline may include a first trace and a second trace that are broadside coupled to each other over at least a portion of the differential stripline to form a broadside coupled portion of the differential stripline. The first trace may be coupled to the first via and may have a first-trace length. The second trace may be coupled to the second via and may have a second-trace length. The broadside coupled portion of the differential stripline may be offset from a plane intersecting substantially half-way between the first via and the second via such that the second-trace length is shorter than the first-trace length.