Patents by Inventor Yasuo Imaeda

Yasuo Imaeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5830777
    Abstract: A compact capacitance type acceleration sensor in which a mass portion having a plurality of movable electrodes are arranged in a recess portion formed on the surface of a p-type single crystal silicon base plate under the condition that the mass portion can be displaced. A plurality of stationary electrodes are arranged at a position opposed to the movable electrodes being separate from the movable electrodes. The mass portion is elastically supported by a support from the lower side and also elastically supported by four beams from the lateral side. Due to the above structure, the damping characteristic of the mass portion can be improved.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: November 3, 1998
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Tatsuya Ishida, Yasuo Imaeda
  • Patent number: 5594271
    Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: January 14, 1997
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Hitoshi Iwata, Koichi Jinkai, Yasuo Imaeda
  • Patent number: 5594171
    Abstract: A compact capacitance type acceleration sensor in which a mass portion having a plurality of movable electrodes are arranged in a recess portion formed on the surface of a p-type single crystal silicon base plate under the condition that the mass portion can be displaced. A plurality of stationary electrodes are arranged at a position opposed to the movable electrodes being separate from the movable electrodes. The mass portion is elastically supported by a support from the lower side and also elastically supported by four beams from the lateral side. Due to the above structure, the damping characteristic of the mass portion can be improved.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: January 14, 1997
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Tatsuya Ishida, Yasuo Imaeda
  • Patent number: 5506439
    Abstract: An object of this invention is to make it possible to directly monitor a temperature of a transistor chip. According to the present invention, p.sup.- region is formed on a substrate of a p.sup.+ layer by epitaxial growth. A first n-type diffusion layer which is a base region, and a second n-type diffusion layer which forms a temperature detecting element are formed in the p.sup.- region. A first p.sup.+ diffusion layer which is an emitter region is formed in the first n-type diffusion layer, while a second p.sup.+ diffusion layer which forms the temperature detecting element is formed in the second n-type diffusion layer. The temperature detecting element is operated in the active region, so that a characteristic free from variations in collector potential is obtained for the base-emitter potential difference of the temperature detecting element and the temperature of the junction thereof.
    Type: Grant
    Filed: August 6, 1992
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Yasuo Imaeda, Hitoshi Iwata, Kenichi Kinoshita
  • Patent number: 5456117
    Abstract: A semiconductor silicon single-crystal substrate is used in which the crystallographic axes are inclined by a predetermined angle with respect to a normal to a thicknesswise face of the semiconductor silicon single-crystal substrate. A conductive-type epitaxial layer is grown on this semiconductor silicon single-crystal substrate to a predetermined thickness such that the direction of the crystallographic axes of the conductive-type epitaxial layer coincides with the direction of the crystallographic axes of the semiconductor silicon single-crystal substrate. Accordingly, since side surfaces of a cavity portion provided in the semiconductor silicon single-crystal substrate by the etching of the substrate, i.e., side walls of the semiconductor silicon single-crystal substrate provided respectively in the longitudinal direction of a diaphragm, are each formed at an angle of 90.degree. with respect to the thicknesswise lower surface of the conductive-type epitaxial layer.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: October 10, 1995
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Yasuo Imaeda, Shigekazu Yasuda, Hitoshi Iwata
  • Patent number: 5296732
    Abstract: A bipolar transistor of the multi-emitter type which is provided with a large number of emitter diffusion layers formed in the two-dimensionally arranged state on a base diffusion layer of a substrate, a large number of emitter electrode films formed respectively correspondingly on the emitter diffusion layers, a base electrode film formed on the base diffusion layer, and a collector electrode film formed on the substrate, and the transistor is further provided with a wiring film commonly connected to the large number of emitter electrode films except at least one of the emitter electrode films.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: March 22, 1994
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Hitoshi Iwata, Koichi Jinkai, Yasuo Imaeda
  • Patent number: 5084751
    Abstract: A bipolar transistor of a multi-emitter construction comprises a base diffusion layer formed in a substrate, a number of emitter diffusion layers formed in the base diffusion layer and arranged in a two-dimensional pattern, a base electrode film formed on the base diffusion layer, the base electrode film having a branch connection portion of a mesh-like shape surrounding each group consisting of at least one of the emitter diffusion layers, the base electrode film also having a main connection portion connected to said branch connection portion, and emitter electrode films formed respectively on said emitter electrode layers.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: January 28, 1992
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Hitoshi Iwata, Yasuo Imaeda, Koichi Jinkai, Kenichi Kinoshita