Patents by Inventor Yasuo Inbe

Yasuo Inbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device and wiring arranging method thereof
    Patent number: 6962868
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Patent number: 6844630
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Publication number: 20040227161
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 18, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei
  • Semiconductor integrated circuit device and wiring arranging method thereof
    Publication number: 20020117757
    Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 29, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Sakamoto, Yasuo Inbe, Masakazu Yaginuma, Kazunari Horikawa, Toshikazu Sei