Abstract: A unidirectional DC-DC converter and method of control thereof. The converter includes a DC power-supply, a buck converter circuit having a first main switching element, a boost converter circuit having a second main switching element, a first snubber capacitor, a first inversely-parallel diode, a control device, and an output diode.

Abstract: A unidirectional DC-DC converter and method of control thereof. The converter includes a DC power-supply, a buck converter circuit having a first main switching element, a boost converter circuit having a second main switching element, a first snubber capacitor, a first inversely-parallel diode, a control device, and an output diode.

Abstract: A unidirectional DC-DC converter which has a simple control circuit without using multiple insulated power supplies or a transformer, uses an auxiliary inductor of a comparatively small capacitance, reduces the size and weight of the converter, and has a very great capacitance without switching of supply current. For example, a unidirectional DC-DC converter equipped with main IGBT101 which supplies and shuts off current for first inductor 108a and diode 107 which discharges energy from main inductor 108a to an the output. The DC-DC converter is further equipped with auxiliary IGBT104 which applies current to back-to-back-connected diode 102 by using energy stored in auxiliary inductor 108b which is magnetically coupled with main inductor 108a. This applies current to the back-to-back-connected diode in a short period including a time period in which the first switching element is turned on and accomplishes ZVZCS.

Abstract: A soft switching DC-DC converter is provided which includes circuitry for both a buck converter and a boost converter. The buck converter circuitry and the boost converter circuitry share a common transformer including a primary coil and first and second secondary coils. A first switching element is coupled to a first capacitor to provide the buck converter operation while another switching element is provided to provide the boost converting operation. The primary coil of the transformer is commonly used as a choke coil by both the buck converter and the boost converter. In this way, size and cost reduction can be obtained.

Abstract: A buck converter circuit and a boost converter circuit, which co-use a main inductor, are connected in series with each other between a DC power-supply and a DC load between output terminals a-b of a rectifier circuit. Moreover, utilizing energy accumulated into first and second auxiliary inductors which are loosely coupled to the main inductor magnetically, a current is flown through diodes during a short time-period including a point-in-time at which main switching elements of the buck and boost converter circuits are to be turned ON. Here, the diodes are connected in inversely parallel to the main switching elements.

Abstract: A unidirectional DC-DC converter which has a simple control circuit without using multiple insulated power supplies, uses an auxiliary inductor of a comparatively small capacitance, reduces the size and weight of the converter, and has a very great capacitance without switching of supply current. A unidirectional DC-DC converter equipped with main IGBT101 which supplies and shuts off current for first inductor 108a and diode 107 which discharges energy from main inductor 108a to an output, wherein the DC-DC converter is further equipped with auxiliary IGBT104 which applies current to back-to-back-connected diode 102 by using energy stored in auxiliary inductor 108b which is magnetically coupled with main inductor 108a. This applies current to the back-to-back-connected diode in a short period including a time period in which the first switching element is turned on and accomplishes ZVZCS.

Abstract: The present invention relates to a soft switching DC-DC converter. A soft switching DC-DC converter comprises a first switching element having a first terminal connected to an input side and having a control terminal for controlling a main electric current; a first diode having a first terminal connected to a second terminal of this first switching element; a primary coil of a transformer having primary and secondary coils, connected to the second terminal of the first switching element; a second diode having a first terminal connected to the first terminal of the first switching element; a second switching element having a first terminal connected to the second terminal of this second diode; and the secondary coil of the transformer, having a first terminal connected to a second terminal of this second switching element, and having a second terminal connected to the second terminal of the first switching element.

Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.

Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal.

Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.

Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal.

Abstract: There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.

Abstract: In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines.

Abstract: There is provided an input/output device which is capable of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal thereof. An expansion device 800 includes an electronic circuit 400 and a MOS switch 300 and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 is coupled to two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state; and, inside the expansion device, the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.

Abstract: An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first volta

Abstract: The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form.

Abstract: The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.

Abstract: The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors.