Patents by Inventor Yasuo Kasagi
Yasuo Kasagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11778818Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.Type: GrantFiled: July 21, 2020Date of Patent: October 3, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Ryo Mochizuki, Yasuo Kasagi, Michiaki Sano, Junji Oh, Yujin Terasawa, Hiroaki Namba
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Publication number: 20220028879Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Inventors: Ryo MOCHIZUKI, Yasuo KASAGI, Michiaki SANO, Junji OH, Yujin TERASAWA, Hiroaki NAMBA
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Patent number: 10381373Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.Type: GrantFiled: September 29, 2017Date of Patent: August 13, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Yasuchika Okizumi, Michiru Hirayama, Naoto Norizuki, Satoshi Shimizu, Yasuo Kasagi, Kimiaki Naruse
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Patent number: 10381443Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.Type: GrantFiled: May 10, 2018Date of Patent: August 13, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Publication number: 20180366487Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.Type: ApplicationFiled: September 29, 2017Publication date: December 20, 2018Inventors: Yasuchika Okizumi, Michiru Hirayama, Naoto Norizuki, Satoshi Shimizu, Yasuo Kasagi, Kimiaki Naruse
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Publication number: 20180261671Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.Type: ApplicationFiled: May 10, 2018Publication date: September 13, 2018Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Patent number: 10020363Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.Type: GrantFiled: March 14, 2017Date of Patent: July 10, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Patent number: 10008570Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.Type: GrantFiled: March 14, 2017Date of Patent: June 26, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Kento Kitamura, Tong Zhang, Chun Ge, Yanli Zhang, Satoshi Shimizu, Yasuo Kasagi, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Johann Alsmeier, James Kai
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Patent number: 9991282Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.Type: GrantFiled: December 15, 2017Date of Patent: June 5, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Satoshi Shimizu, Hiroyuki Ogawa, Yasuo Kasagi, Kento Kitamura
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Publication number: 20180151589Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.Type: ApplicationFiled: December 15, 2017Publication date: May 31, 2018Inventors: Satoshi SHIMIZU, Hiroyuki OGAWA, Yasuo KASAGI, Kento KITAMURA
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Patent number: 9985098Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.Type: GrantFiled: March 14, 2017Date of Patent: May 29, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Publication number: 20180122905Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.Type: ApplicationFiled: March 14, 2017Publication date: May 3, 2018Inventors: Hiroyuki Ogawa, Yasuo Kasagi, Satoshi Shimizu, Kazuyo Matsumoto, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Publication number: 20180122904Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.Type: ApplicationFiled: March 14, 2017Publication date: May 3, 2018Inventors: Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Hiroyuki Ogawa, Yohei Masamori, Jixin Yu, Tong Zhang, James Kai
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Publication number: 20180122906Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.Type: ApplicationFiled: March 14, 2017Publication date: May 3, 2018Inventors: Jixin YU, Kento KITAMURA, Tong ZHANG, Chun GE, Yanli ZHANG, Satoshi SHIMIZU, Yasuo KASAGI, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Johann ALSMEIER, James KAI
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Patent number: 9876031Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.Type: GrantFiled: January 30, 2017Date of Patent: January 23, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Satoshi Shimizu, Hiroyuki Ogawa, Yasuo Kasagi, Kento Kitamura
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Patent number: 5773890Abstract: A titanium film 14 is formed on a whole surface including an inner surface of a hole 10. Then the titanium film 14 outside of the interior of the hole 10 is removed by the chemical mechanical polishing (CMP) method, the resist etchback method or the ECR plasma etching method. Thereafter a titanium nitride film 15 is formed on the whole surface. Consequently, when a tungsten film 16 is formed, using a fluorine containing gas such as WF.sub.6 gas, etc., since there exists no titanium film 14 outside of the hole 10 and only the titanium nitride film 15 resistant to the fluorine containing gas exists there, no peeling-off of the titanium nitride film 15 due to corrosion of the titanium film 14 takes place, and thus it is prevented that it produces a dust source.Type: GrantFiled: August 27, 1996Date of Patent: June 30, 1998Assignee: Nippon Steel CorporationInventors: Tomoyuki Uchiyama, Yasuo Kasagi
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Patent number: 5672907Abstract: A semiconductor device in which the elution quantity of boron and phosphorus from a BPSG film in a process of washing a wafer is controlled low so as to realize sufficient flattening and in which a reflow processing temperature is lowered by increasing concentrations of boron and phosphorus in the BPSG film. A first BPSG film in which the boron concentration is 3.5 wt % to 4.5 wt % and the phosphorus concentration is 5.5 wt % to 6.5 wt % is formed through a polysilicon wiring layer on a semiconductor substrate by a CVD method using an inorganic material source such as SiH.sub.4, B.sub.2 H.sub.6, PH.sub.3, O.sub.2 or an organic material source such as TEOS, TMOP, TMB, or O.sub.3. A gas flow rate is then changed so as to form a second BPSG film having a boron concentration of 2.0 wt % to 3.0 wt % and a phosphorus concentration of 5.5 wt % to 6.5 wt %.Type: GrantFiled: March 19, 1996Date of Patent: September 30, 1997Assignee: Nippon Steel CorporationInventor: Yasuo Kasagi
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Patent number: 5502006Abstract: When taper portions of contact holes are etched to form wiring conductors in a semiconductor device, a hydrophobic insulating film having methyl groups on its surface is formed on a SiO.sub.2 film in the low pressure CVD process, using mixed gas of tetraethyl orthosilicate TEOS and ozone O.sub.3. Since the hydrophobic insulating film adheres well to a resist film, etching solution seldom soaks into between the hydrophobic insulating film and the resist film, thus wet etching is performed in the insulating film to obtain satisfactory taper portions of the contact holes.Type: GrantFiled: November 2, 1994Date of Patent: March 26, 1996Assignee: Nippon Steel CorporationInventor: Yasuo Kasagi