Patents by Inventor Yasuo Kiguchi

Yasuo Kiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabrication of semiconductor integrated circuit device
    Patent number: 7098156
    Abstract: The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel at high speed on conveying rails laid on the floor of the clean room. A structure is adopted wherein a conveying area, over which the RGV travels, is separated from a human working area by a compartment (partition), and a human is not allowed to enter the conveying area upon operation of a line.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: August 29, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Wakabayashi, Toshiyuki Uchino, Yasuo Kiguchi, Atsuyoshi Koike
  • Method of fabrication of semiconductor integrated circuit device
    Publication number: 20040166689
    Abstract: The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel on conveying rails (3) laid on the floor of the clean room at high speed. A structure is adopted wherein a conveying area over which the RGV travels, is separated from a human working area by a compartment (partition) (4), and a human does not enter the conveying area upon operation of a line.
    Type: Application
    Filed: April 15, 2004
    Publication date: August 26, 2004
    Inventors: Takayuki Wakabayashi, Toshiyuki Uchino, Yasuo Kiguchi, Atsuyoshi Koike
  • Semiconductor integrated circuit device
    Patent number: 6512245
    Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: January 28, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
  • Semiconductor memory device having driver and load MISFETs and capacitor elements
    Patent number: 6307217
    Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: October 23, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
  • Semiconductor integrated circuit device
    Publication number: 20010023965
    Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
    Type: Application
    Filed: May 17, 2001
    Publication date: September 27, 2001
    Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
  • Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
    Patent number: 5917211
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 29, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
    Patent number: 5734188
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
  • Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
    Patent number: 5264712
    Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
    Type: Grant
    Filed: May 7, 1992
    Date of Patent: November 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi