Patents by Inventor Yasuo Koutake

Yasuo Koutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6989590
    Abstract: A power semiconductor device according to the present invention comprises at least one insulating substrate; at least one power semiconductor element mounted on a metal pattern formed on the main surface of the insulating substrate; and a control circuit board which is arranged so that its first surface can oppose the above main surface of the insulating substrate with the power semiconductor element interposed therebetween, and which has at least one electronic component for control, mounted on a metal pattern formed on its second surface in parallel to the above first surface, and at least one through hole formed vertically to the first and second surfaces so as to electrically connect circuit patterns laminated between the first surface and the second surface, and this power semiconductor device is characterized in that the above through hole is filled with a filler.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: January 24, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hironobu Hanada, Yasuo Koutake
  • Publication number: 20050012198
    Abstract: A power semiconductor device according to the present invention comprises at least one insulating substrate; at least one power semiconductor element mounted on a metal pattern formed on the main surface of the insulating substrate; and a control circuit board which is arranged so that its first surface can oppose the above main surface of the insulating substrate with the power semiconductor element interposed therebetween, and which has at least one electronic component for control, mounted on a metal pattern formed on its second surface in parallel to the above first surface, and at least one through hole formed vertically to the first and second surfaces so as to electrically connect circuit patterns laminated between the first surface and the second surface, and this power semiconductor device is characterized in that the above through hole is filled with a filler.
    Type: Application
    Filed: March 8, 2004
    Publication date: January 20, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hironobu Hanada, Yasuo Koutake
  • Patent number: 6642576
    Abstract: An IGBT (121) and a diode (131) are joined onto an element arrangement portion (111a) of a first terminal member (111) and an element arrangement portion (112a) of a second terminal member (112) is joined onto the IGBT (121) and the diode (131). Further, an IGBT (122) and a diode (132) are joined onto the element arrangement portion (112a) of the second terminal member (112) and an element arrangement portion (113a) of a third terminal member (113) is joined onto the IGBT (122) and the diode (132). A transfer mold package (141) is so formed as to house the elements (121, 122, 131, 132). External connection portions (111b, 112b, 113b) of the terminal members (111, 112, 113) are drawn out of the package (141). The element arrangement portion(s) (111a, 113a) of the first and/or third terminal member (111, 113) are/is exposed out of the package (141).
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: November 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaaki Shirasawa, Yasuo Koutake, Tsuyoshi Takayama, Natsuki Tsuji