Abstract: A unit address is automatically set in a peripheral unit. A plurality of peripheral units 1 are connected to a CPU unit via a signal line 3. The CPU unit accesses each peripheral unit 1 by individually selecting the peripheral units. The signal line 3 is provided with a first signal line 31 for transmitting an address by bus connection of the peripheral units and a second signal 32 line for transmitting a write command signal by cascade connection of the peripheral units 1. The write command signal is sequentially transmitted in the order in which the peripheral units 1 are connected, and only the peripheral unit 1 that has received the write command signal receives a unit address and retains it in a latch circuit 11a.

Abstract: A multi-CPU system comprises between a CPU without a control terminal and a common memory: an access mediation latch for temporarily latching data information to be transferred and corresponding address information; and a timing control circuit for controlling the timing of data transfer between the access mediation latch and the common memory in accordance with a mediation signal outputted from a contention mediation terminal of the common memory.