Patents by Inventor Yasuo Moriguchi

Yasuo Moriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7148567
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a–40e, 41a–41e and 42a–42d), a plurality of LEADs (50a–50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a–60e and 61a–61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a–40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a–50d).
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: December 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Publication number: 20050156305
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).
    Type: Application
    Filed: March 14, 2005
    Publication date: July 21, 2005
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Patent number: 6674623
    Abstract: In a microcomputer equipped with a built-in temperature sensor, diodes as a temperature sensor are incorporated in a pair of circuit blocks, respectively, and placed in opposite polarity connection to each other. When detecting a temperature of the microcomputer, a constant current If is supplied to the diodes through terminals commonly connected to both the diodes. A voltage Vf generated at each diode is read through terminals located at more adjacent nodes to the diode when compared in position with the terminals.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: January 6, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Abe, Shintaro Mori, Fumihiko Terayama, Masahiro Kitamura, Seiichi Yamazaki, Yasuo Moriguchi
  • Publication number: 20030102556
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).
    Type: Application
    Filed: June 4, 2002
    Publication date: June 5, 2003
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Patent number: 6333643
    Abstract: A hotplug tolerant I/O circuit, which is incorporated in a first device, includes a voltage generator. In a hotplug mode, in which an input signal higher than the power supply voltage is applied from a second device to the first device while the power supply voltage is not applied to the first device, the voltage generator generates a control voltage from the input signal, and supplies it to a transistor in the hotplug tolerant I/O circuit. This makes it possible to solve a problem of a conventional hotplug tolerant I/O circuit in that the transistors in the I/O circuit can be damaged in the hotplug mode.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: December 25, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuaki Kurooka, Yasuo Moriguchi
  • Patent number: 6170072
    Abstract: There is constituted a logic circuit verification apparatus designed for checking a semiconductor integrated circuit including a core and a new circuit. The core has a internal circuit in which logic and timing have already been verified. The apparatus is provided with a section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit. The apparatus is also provided with a section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit. At the time of simulation, predetermined processing is performed solely with regard to the extracted cells.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: January 2, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Moriguchi, Toshinori Inoshita, Yoshio Inoue
  • Patent number: 6088821
    Abstract: A logic verification apparatus for a semiconductor integrated circuit classifies a program described in HDL into connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion, converts a portion of the connection information of the asynchronous circuit portion into the connection information of the synchronous circuit portion and increases circuit portions the function of which can be verified by a cycle based simulation/static timing verification unit, thus making it possible to shorten the time for verification.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: July 11, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Moriguchi, Hiroyuki Mori, Yoshio Inoue, Toshinori Inoshita
  • Patent number: 5510141
    Abstract: The invention relates to a method for applying a coating composition to a substrate with a reverse roller coater so as to form a thin film on the substrate and then for baking the thin film so as to transform the thin film into a metal oxide film. The coating composition comprises: 0.1-10 wt % of at least one organic metal compound on a metal oxide basis; and at least one organic solvent. The at least one organic metal compound is selected from the group consisting of metal alkoxides, metal acetyl-acetonates and metallic soaps. The coating composition is adjusted to have a viscosity within a range from 0.1 to 100 centipoises. In this method, a reverse roller of the coater is rotated at a rotation speed within a range from 2 to 55 m/min. and the substrate is moved at a moving speed within a range from 1 to 30 m/min. while the coating composition is applied to the substrate. Furthermore, the rotation speed of the reverse roller is adjusted to be higher than the moving speed of the substrate.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: April 23, 1996
    Assignee: Central Glass Company, Limited
    Inventors: Kensuke Makita, Yasuo Moriguchi, Junichi Okuda
  • Patent number: 5338350
    Abstract: An ink composition for forming a thin metal oxide film contains a glass component, a viscosity-increasing agent and a solvent. The glass component is one of a halogen-containing metal alkoxide, a mixture of the halogen-containing metal alkoxide and another metal alkoxide, and a mixture of the halogen-containing metal alkoxide and a metal oxide sol. The viscosity-increasing agent is nitrocellulose H60 according to Japanese Industrial Standard K6703. The solvent is at least one of ethylcarbitol and butylcarbitol. The formed thin metal oxide film is superior in transparency, abrasion resistance and scratch resistance.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: August 16, 1994
    Assignee: Central Glass Company, Limited
    Inventors: Katsuto Tanaka, Kensuke Makita, Yasuo Moriguchi
  • Patent number: 5137749
    Abstract: The invention relates to a sol-gel method for forming a metal oxide film, e.g. TiO.sub.2 film or TiO.sub.2 -SiO.sub.2 film, on a substrate by applying a solution of at least one metal alkoxide to the substrate to form a sol film on the substrate, drying the sol film to cause it to turn into a gel film by hydrolysis and baking the gel film. According to the invention the viscosity of the metal alkoxide solution is adequately increased, preferably to 3-30 cP at 20.degree. C., by the addition of a combination of a hydroxypropyl cellulose of which 2 wt % aqueous solution has a viscosity of 150-400 cP at 20.degree. C. and another hydroxypropyl cellulose of which 2 wt % aqueous solution has a viscosity of 6-10 cP at 20.degree. C. Metal oxide films formed by this method are free from minute cracks and excellent in optical characteristics and durability. By this method it is possible to form a metal oxide film as thick as about 300 nm without repeating the application of the alkoxide solution to the substrate.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: August 11, 1992
    Assignee: Central Glass Company, Limited
    Inventors: Seizi Yamazaki, Kensuke Makita, Yasuo Moriguchi, Katsuto Tanaka
  • Patent number: 4398406
    Abstract: A method for producing cold rolled titanium strips having good surface quality. The cold rolling of a titanium strip is carried out under the conditions represented by the following formula:X.ltoreq.(48673/Y.sup.1.3283)where X is an average grain size (.mu.m) of the pre-cold rolled titanium strip and Y is a diameter (mm) of the roll for the cold rolling.
    Type: Grant
    Filed: May 18, 1981
    Date of Patent: August 16, 1983
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Masahito Fukuda, Akiyoshi Tanabe, Yasuo Moriguchi, Nobuyuki Nagai, Kunio Tsuji, Yoshihiro Yamaguchi, Tomiharu Matsushita, Atsuo Mizuta
  • Patent number: 4167427
    Abstract: In a process for heat treating titanium alloys, and .alpha.+.beta. titanium alloy, heated and held in a temperature range above 500.degree. C. and below the .alpha.+.beta./.beta. transformation point, and then quenched, is further aged at a low temperature in the range between 50.degree. and 300.degree. C.
    Type: Grant
    Filed: October 18, 1977
    Date of Patent: September 11, 1979
    Assignees: Mitsubishi Jukogyo Kabushiki Kaisha, Kobe Steel, Ltd.
    Inventors: Shoji Ueda, Takashi Daikoku, Yorimasa Takeda, Akira Hiromoto, Nobuyuki Nagai, Yasuo Moriguchi, Yoshimasa Ito
  • Patent number: 4134758
    Abstract: A titanium alloy having a high degree of internal friction and suitable for rotating blades of turbomachines is composed of 5.5 - 6.75% Al, 1 - 5% V, 1 - 5% Mo, V plus Mo being greater than or equal to 5%, and the balance Ti and usual impurities, all by weight. A method of heat-treating the alloy comprises maintaining the same at a temperature not lower than 125.degree. C below its .beta. transformation point for a predetermined period of time and then rapidly cooling the alloy.
    Type: Grant
    Filed: April 26, 1977
    Date of Patent: January 16, 1979
    Assignees: Mitsubishi Jukogyo Kabushiki Kaisha, Kobe Steel, Ltd.
    Inventors: Nobuyuki Nagai, Yasuo Moriguchi, Yoshimasa Itoh, Shoji Ueda, Yorimasa Takeda, Akira Hiromoto