Patents by Inventor Yasuo Nara

Yasuo Nara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8883577
    Abstract: A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yasuo Nara
  • Publication number: 20100167475
    Abstract: A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator.
    Type: Application
    Filed: December 16, 2009
    Publication date: July 1, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Yasuo Nara
  • Patent number: 7465980
    Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: December 16, 2008
    Assignees: Fujitsu Limited, Tokyo Institute of Technology
    Inventors: Yoshihiro Arimoto, Hiroshi Ishihara, Tetsuro Tamura, Hiromasa Hoko, Koji Aizawa, Yoshiaki Tabuchi, Masaomi Yamaguchi, Yasuo Nara, Kazuhiro Takahashi, Satoshi Hasegawa
  • Publication number: 20060081901
    Abstract: A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.
    Type: Application
    Filed: September 8, 2005
    Publication date: April 20, 2006
    Applicants: FUJITSU LIMTED, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Yoshihiro Arimoto, Hiroshi Ishihara, Tetsuro Tamura, Hiromasa Hoko, Koji Aizawa, Yoshiaki Tabuchi, Masaomi Yamaguchi, Yasuo Nara, Kazuhiro Takahashi, Satoshi Hasegawa
  • Publication number: 20030222303
    Abstract: A non-volatile semiconductor memory device comprise a source region 44 and a drain region 46 formed in a semiconductor substrate 30; a gate electrode 36 formed on the semiconductor substrate between the source region and the drain region with a first insulation film 32 formed between the gate electrode and the semiconductor substrate; and a charge accumulation region 42a, 42b of a dielectric material, which is formed on at least either of the side wall of the gate electrode on the side of the source region and the side wall of the gate electrode on the side of the drain region. Accordingly, charges accumulated on the side of the source region 44 and the charges accumulated on the side of the drain region 46 can be easily spatially isolated from each other.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 4, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masatoshi Fukuda, Taro Sugizaki, Toshiro Nakanishi, Yasuo Nara
  • Patent number: 5276724
    Abstract: Several ten thousands or several millions of juxtaposed hollow thin tubes, each having a diameter of, for example, 12 .mu.m and a length of 1 mm, are joined to each other to form a window having a predetermined open surface area. The window having a diameter of, for example, 30 mm, can withstand a differential pressure of several atm. A high-vacuum X-ray source and the window consisting of thin tubes having the aforementioned dimensions are connected through a differential evacuating device having a plurality of stages connected with a partitioning wall having an orifice of predetermined dimensions provided between the adjacent stages. The pressures at the two sides of the window are maintained to the atmospheric pressure and a pressure which is 1/10th of the atmospheric pressure, respectively. X-rays having a long wavelength of 10 .ANG.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: January 4, 1994
    Assignee: Fujitsu Limited
    Inventors: Fumiaki Kumasaka, Yoshimi Yamashita, Kei Horiuchi, Yasuo Nara
  • Patent number: 5225355
    Abstract: A gettering treatment process comprises the step of irradiating an ultraviolet light onto an insulating layer (a silicon oxide thin layer formed by thermally oxidizing silicon), in a chlorine-containing gas atmosphere. The ultraviolet light excites and dissociates the chlorine-containing gas thereby to generate chlorine radicals which uniformly penetrate the insulating layer, and serve to trap metal impurities within the silicon oxide thin layer.
    Type: Grant
    Filed: March 17, 1992
    Date of Patent: July 6, 1993
    Assignee: Fujitsu Limited
    Inventors: Rinshi Sugino, Yasuo Nara, Takashi Ito