Abstract: Data having an ID code attached thereto is transferred via a network line. The ID code is detected by an ID code detection circuit and data is received by a data receiving circuit. An ID code detected by the ID code detection circuit and an ID code previously stored in an ID comparing register are compared with each other by a comparator circuit. Predetermined ID codes corresponding to an engine rotation speed and car speed, for example, are stored in the ID comparing register. A masking circuit for masking one or more bits of the ID code is provided in the comparator circuit. The switching state of a switch for controlling the transfer of data received by the data receiving circuit is controlled according to a comparison output of the comparator circuit. When the ID codes are coincident with each other, the switch is turned on, causing data received by the data receiving circuit to be transferred to a CPU.

Abstract: An apparatus which is inserted in a signal transmission path between a network communications cable and a sending and receiving circuit. The apparatus enables switching of the connection polarity of the communications cable. This apparatus has an idle status detection section, a judgment section which responds to an idle status detection of the idle status detection section and judges the polarity of the communications cable on the basis of a signal level of the communications cable, and a polarity switching section which switches the polarity of the signal send and receive in accordance with a polarity indicated by polarity judgment signals output from the judgment portion. The use of this apparatus eliminates the necessity to recognize the polarity when connection work is performed, and simplifies the connection work itself.

Abstract: A power voltage drop detecting circuit includes VDD and ground terminals supplied with power voltage VD, a resistor connected at one end to the VDD terminal, a MOS transistor connected between the other end of the resistor and the ground terminal, and a CMOS inverter for producing an output signal according to a voltage at the junction between the resistor and the MOS transistor. The detecting circuit further includes a control pad connected to the control gate of the n-channel MOS transistor and supplied with control voltage VC at different levels in the test mode and detect modes, respectively.