Patents by Inventor Yasuo Ohno

Yasuo Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6248357
    Abstract: A solid pharmaceutical preparation comprising a pharmaceutically active ingredient, erythritol, crystalline cellulose and an disintegrants, which exhibits a fast buccal disintegratability and dissolubility.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: June 19, 2001
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Yasuo Ohno, Tadashi Makino, Junichi Kikuta
  • Patent number: 6180968
    Abstract: There are provided a compound semiconductor device having a semiconductor multilayered structure, and a method of manufacturing the same. The semiconductor multilayered structure consists of a first recess etching stopper formed on a conductive layer of a compound semiconductor, a first semiconductor layer formed on the first recess etching stopper layer, a second recess etching stopper layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second recess etching stopper layer.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: January 30, 2001
    Assignee: NEC Corporation
    Inventors: Kensuke Kasahara, Yasuo Ohno, Satoru Ohkubo
  • Patent number: 6121641
    Abstract: A p-type layer which is not depleted is inserted in a position at a depth relative to a lower surface of a gate electrode that is less than three times the distance between a lower surface of a gate electrode and a channel layer. A drain voltage at which the p-type layer is depleted is higher than a drain voltage at which a speed of electrons is saturated for thereby shielding traps while suppressing a drain parasitic capacitance and a short channel effect.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventor: Yasuo Ohno
  • Patent number: 6075263
    Abstract: A method of evaluating the surface/interface of a semiconductor device is disclosed. This method uses the semiconductor device in which an n-type source electrode and an n-type drain electrode are formed on both ends of the surface of an n-type conductive layer formed on a semiconductor substrate; and a gate electrode composed of a p-type ohmic electrode or an n-type Schottky electrode is formed on one end of the surface on which the source or drain electrode is not disposed. In this semiconductor device, voltage to be applied to the gate electrode is changed and a change of current flowing between the source electrode and the drain electrode in response to the voltage change is measured. Then the type of trap on the surface/interface of the semiconductor is determined from an amount of change in the value of the current.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventors: Yuji Takahashi, Yasuo Ohno
  • Patent number: 5958453
    Abstract: A solid pharmaceutical preparation comprising a pharmaceutically active ingredient, erythritol, crystalline cellulose and an disintegrants, which exhibits a fast buccal disintegratability and dissolubility.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: September 28, 1999
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Yasuo Ohno, Tadashi Makino, Junichi Kikuta
  • Patent number: 5949096
    Abstract: In a field effect transistor, a semiconductor channel layer is formed for carriers to run therein, and a first conductive semiconductor carrier supply layer is formed on the channel layer. Also, a second conductive semiconductor layer has a conductive type opposite to the carrier supply layer or contacts the gate electrode and is formed of same materials as the carrier supply layer. A third conductive semiconductor layer is formed on the layer having a conductive type opposite to the carrier supply layer or contacting the gate electrode and has the same conductive type of the carrier supply layer. A schottky gate electrode is formed in contact with the second conductive semiconductor layer.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventors: Satoru Ohkubo, Yasuo Ohno, Kazuaki Kunihiro
  • Patent number: 5891757
    Abstract: A field-effect transistor has a source region, a drain region, a gate electrode, and a low resistivity layer. The source and drain regions are of a first conductivity type and formed as surface regions of a semiconductor layer formed on one of an insulating substrate and a semi-insulating substrate. The gate electrode is formed on a channel region between the source region and the drain region. The low resistivity layer serving as a shield layer is disposed underneath and spaced apart from the source, drain and channel regions, and overlaps the source region with an overlap area being larger than an overlap area between the low resistivity layer and the drain region. The arrangement enables the prevention of noise margin reduction and erroneous operation.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: April 6, 1999
    Assignee: NEC Corporation
    Inventor: Yasuo Ohno
  • Patent number: 5619146
    Abstract: In a switching speed fluctuation detecting apparatus, an input terminal for receiving a signal having a definite time period, a series arrangement of at least one first logic circuit connected to the input terminal, a second logic circuit having a first input connected to the input terminal and a second input connected to an output of the series arrangement and an integrator connected to an output of the second logic circuit are provided.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: April 8, 1997
    Assignee: NEC Corporation
    Inventors: Masahiro Fujii, Yasuo Ohno, Tadashi Maeda, Takao Atsumo, Noriaki Matsuno, Keiichi Numata, Nobuhide Yoshida
  • Patent number: 5389802
    Abstract: In an n-channel heterojunction field effect transistor (HJFET) comprising a buffer region, a channel layer, and a carrier supplying layer which are deposited on a substrate in this order, the buffer region comprises a p-type GaAs layer, an undoped GaAs layer, and an n-type GaAs layer in this order. The p-type GaAs layer has substantially the same impurity concentration per unit area as the n-type GaAs layer. Holes are depleted in the whole of the buffer region at thermal equilibrium.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 14, 1995
    Assignee: NEC Corporation
    Inventor: Yasuo Ohno
  • Patent number: 4831422
    Abstract: A field effect transistor having a short channel length of 1 .mu.m or less is disclosed. The transistor includes a plurality of impurity regions provided in the channel region between the source and drain regions. The impurity region has the same conductivity type as the channel produced between the impurity regions and a higher impurity density than the carrier density of the channel so that the heat in the carriers is transferred laterally to the impurity regions.
    Type: Grant
    Filed: February 13, 1986
    Date of Patent: May 16, 1989
    Assignee: NEC Corporation
    Inventor: Yasuo Ohno
  • Patent number: 4552312
    Abstract: A fuel injection valve has a collar-shaped stopper at the front of a plunger for restricting the plunger stroke between the stopper and the end of a guide pipe. The divergent conical surface or spherical surface is formed at the end of the guide pipe, a spherical surface which makes contact with the conical surface is formed at the opposite side of the stopper of the plunger to the ball, an automatic centering operation is performed at the stroke end of the plunger, thereby preventing the irregular wear of the ball valve and the seat surface to stabilize the performance for a long period of time.
    Type: Grant
    Filed: January 9, 1984
    Date of Patent: November 12, 1985
    Assignee: Tohoku Mikuni Kogyo Kabushiki Kaisha
    Inventors: Yasuo Ohno, Tadashi Seino, Yukio Ueno, Kenji Kariyama, Shinji Utsugi, Shigeo Okada
  • Patent number: 4530001
    Abstract: The semiconductor device comprises a semiconductor substrate, a plurality of spaced active elements, for example, of a planer type formed on one surface of the substrate, and a supporting plate bonded to the opposite surface of the substrate. A groove is cut through the substrate to reach the supporting plate for isolating the active elements.
    Type: Grant
    Filed: September 15, 1981
    Date of Patent: July 16, 1985
    Assignees: Oki Electric Industry Co., Ltd., Nippon Telegraph & Telephone Public Corp.
    Inventors: Haruo Mori, Yasuo Ohno, Yutaka Ohta, Hiroshi Tanabe, Kotaro Kato