Patents by Inventor Yasuo Osone

Yasuo Osone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263559
    Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 16, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 8937390
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Publication number: 20140361406
    Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 11, 2014
    Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
  • Patent number: 8860093
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 14, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Publication number: 20140183730
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
  • Patent number: 8742499
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
  • Patent number: 8704352
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: April 22, 2014
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Publication number: 20120261799
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
  • Patent number: 8227836
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: July 24, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 7905149
    Abstract: There is provided a physical sensor which ensures long-term reliability and can be miniaturized and increased in density, and a method of producing the same. A physical sensor includes a supporting substrate, an element substrate that includes a sensor element and is joined to the supporting substrate through an insulating layer, a glass cap that covers an area of the sensor element and is joined to the element substrate, and a built-in electrode that is electrically connected to the sensor element. The built-in electrode is formed in a through hole passing through the element substrate, the insulating layer and the supporting substrate. A portion of the glass cap that covers an area of the built-in electrode is anodically bonded to the element substrate.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: March 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kengo Suzuki, Takeshi Harada, Yasuo Osone, Masahide Hayashi, Teruhisa Akashi
  • Publication number: 20100171213
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 8, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
  • Publication number: 20100109052
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 6, 2010
    Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE
  • Publication number: 20100032720
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Application
    Filed: October 15, 2009
    Publication date: February 11, 2010
    Inventors: Satoshi SASAKI, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 7656030
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
  • Patent number: 7622756
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 7583163
    Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 1, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
  • Patent number: 7554193
    Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
  • Publication number: 20090020419
    Abstract: There is provided a physical sensor which ensures long-term reliability and can be miniaturized and increased in density, and a method of producing the same. A physical sensor includes a supporting substrate, an element substrate that includes a sensor element and is joined to the supporting substrate through an insulating layer, a glass cap that covers an area of the sensor element and is joined to the element substrate, and a built-in electrode that is electrically connected to the sensor element. The built-in electrode is formed in a through hole passing through the element substrate, the insulating layer and the supporting substrate. A portion of the glass cap that covers an area of the built-in electrode is anodically bonded to the element substrate.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 22, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Kengo SUZUKI, Takeshi Harada, Yasuo Osone, Masahide Hayashi, Teruhisa Akashi
  • Publication number: 20080129412
    Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.
    Type: Application
    Filed: August 10, 2007
    Publication date: June 5, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
  • Publication number: 20070176298
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 2, 2007
    Applicants: Hitachi, Ltd., Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe