Patents by Inventor Yasuo Otsuka
Yasuo Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955302Abstract: An electromagnetic relay includes a fixed terminal, a movable contact piece, a first contact, and a second contact. The fixed terminal includes a first surface. The movable contact piece includes a second surface disposed to face the first surface. The first contact is embedded in one of the fixed terminal or the movable contact piece to be flush with one of the first surface or the second surface. The second contact is disposed on the other of the fixed terminal or the movable contact piece to face the first contact. The second contact protrudes from the other of the first surface or the second surface toward the first contact and include a contact surface smaller than the first contact when viewed from a direction facing the first contact.Type: GrantFiled: February 18, 2019Date of Patent: April 9, 2024Assignee: OMRON CORPORATIONInventors: Kohei Otsuka, Ryota Minowa, Hiroyuki Iwasaka, Yasuo Hayashida, Shingo Mori, Naoki Kawaguchi
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Patent number: 11942297Abstract: A relay includes a movable contact piece having a movable contact, a fixed contact, a drive device configured to move the movable contact piece, a magnet to apply a Lorentz force to an arc in a first extension direction, a fixed terminal having an intermediate portion to apply a Lorentz force to the arc in a second extension direction, and a wall portion. The wall portion includes first and second wall surfaces. The first wall surface is disposed to face an arc-extinguishing space, and is disposed opposite to the movable contact and the fixed contact in the first extension direction. The second wall surface is disposed to face the arc-extinguishing space and is disposed downstream in the second extension direction with respect to the first wall surface. A distance from the movable contact piece to the second wall surface differs from a distance to the first wall surface.Type: GrantFiled: February 18, 2019Date of Patent: March 26, 2024Assignee: OMRON CORPORATIONInventors: Naoki Kawaguchi, Ryota Minowa, Yasuo Hayashida, Shingo Mori, Kohei Otsuka, Hiroyuki Iwasaka
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Patent number: 11935716Abstract: A relay includes a fixed contact, a movable contact piece including a movable contact, a movable portion, a coil, a return spring, and a contact spring. The movable portion includes a drive shaft and a movable iron core. The drive shaft is fixed to the movable contact piece in a contact case and extends from an inside of the contact case to an outside of the contact case. The movable iron core is connected to the drive shaft outside the contact case. The return spring urges the movable portion in an open direction in which the movable contact is separated from the fixed contact. The contact spring urges the drive shaft in a contact direction in which the movable contact contacts the fixed contact. The contact spring is arranged outside the contact case.Type: GrantFiled: March 4, 2019Date of Patent: March 19, 2024Assignee: OMRON CORPORATIONInventors: Shingo Mori, Ryota Minowa, Yasuo Hayashida, Naoki Kawaguchi, Kohei Otsuka, Hiroyuki Iwasaka
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Patent number: 11901337Abstract: A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.Type: GrantFiled: September 2, 2021Date of Patent: February 13, 2024Assignee: KIOXIA CORPORATIONInventor: Yasuo Otsuka
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Publication number: 20240015991Abstract: According to one embodiment, a memory device is disclosed. The memory device includes a substrate, an on-volatile memory, a memory controller, an interconnect including one end and another end. The one end is connected to the memory controller. A footprint is on the substrate and connected to the another end of the interconnect. An ESD protection element is on the substrate and connected to the footprint. A connection terminal is on the substrate and connectable to a host device. A via plug is in the substrate. One end of the via plug is connected to the another end of the interconnect and another end of the first plug is connected to the connection terminal.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Applicant: Kioxia CorporationInventors: Toshitada SAITO, Yasuo OTSUKA, Atsushi KONDO
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Publication number: 20230110997Abstract: According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.Type: ApplicationFiled: August 26, 2022Publication date: April 13, 2023Inventors: Yasuo OTSUKA, Nobuhito SUZUYA
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Patent number: 11437351Abstract: A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.Type: GrantFiled: February 19, 2021Date of Patent: September 6, 2022Assignee: Kioxia CorporationInventor: Yasuo Otsuka
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Publication number: 20220238490Abstract: A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.Type: ApplicationFiled: September 2, 2021Publication date: July 28, 2022Applicant: Kioxia CorporationInventor: Yasuo OTSUKA
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Publication number: 20220077115Abstract: A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.Type: ApplicationFiled: February 19, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventor: Yasuo OTSUKA
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Patent number: 11037879Abstract: According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.Type: GrantFiled: August 28, 2019Date of Patent: June 15, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuo Otsuka
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Publication number: 20200294922Abstract: According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.Type: ApplicationFiled: August 28, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Yasuo OTSUKA
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Patent number: 7979821Abstract: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.Type: GrantFiled: May 9, 2008Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventor: Yasuo Otsuka
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Patent number: 7832871Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.Type: GrantFiled: October 17, 2008Date of Patent: November 16, 2010Assignee: Hitachi, Ltd.Inventors: Kenji Fuse, Mikio Shiraishi, Yasuo Otsuka, Nobuyuki Kaku, Hidehiro Ikeda
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Patent number: 7571409Abstract: A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library including embedded circuit information, grasps physical positional relationships among elements such as terminals and wires, and checks whether the elements are short-circuited to each other or not. The library including embedded circuit information records a result of placement and routing output by the placement and routing processing unit, attribute information on a test circuit to be embedded into the customer circuit or terminal information and wire position information, and the like on the test circuit. The elements that are short-circuited to each other are incorporated into a netlist to be generated, as the elements constituting one net.Type: GrantFiled: June 29, 2006Date of Patent: August 4, 2009Assignee: NEC Electronics CorporationInventor: Yasuo Otsuka
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Publication number: 20090059180Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.Type: ApplicationFiled: October 17, 2008Publication date: March 5, 2009Inventors: Kenji Fuse, Mikio Shiraishi, Yasuo Otsuka, Nobuyuki Kaku, Hidehiro Ikeda
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Publication number: 20080313585Abstract: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.Type: ApplicationFiled: May 9, 2008Publication date: December 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Yasuo Otsuka
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Patent number: 7441904Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.Type: GrantFiled: January 30, 2007Date of Patent: October 28, 2008Assignee: Hitachi, Ltd.Inventors: Kenji Fuse, Mikio Shiraishi, Yasuo Otsuka, Nobuyuki Kaku, Hidehiro Ikeda
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Patent number: 7327520Abstract: The present invention discloses the structure of the array lens that at least any one of the diagonal size, vertical size and lateral size of lens cell is set to almost 1/(4.5 or more) for each corresponding size of the display elements, the structure that the diagonal size of lens cell is set to almost 0.18 inch or less, the structure that the total number of lens cells is set to almost 240 or more and the structure that the lens focal distance of lens cell is set to almost 30 mm or less.Type: GrantFiled: July 25, 2006Date of Patent: February 5, 2008Assignee: Hitachi, Ltd.Inventors: Satoshi Ohuchi, Masahiko Yatsu, Taro Imahase, Tomohiro Miyoshi, Yasuo Otsuka, Takesuke Maruyama
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Publication number: 20070121082Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Inventors: Kenji Fuse, Mikio Shiraishi, Yasuo Otsuka, Nobuyuki Kaku, Hidehiro Ikeda
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Patent number: 7175284Abstract: A projection type display apparatus includes a housing having a first side having an air intake opening and a second side having an air exhaust opening, a light source for supplying light, and a light valve device which modulates the light output from the light source. A centrifugal fan is associated with the air intake opening so as to draw air from the air intake opening. A first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve, and a second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve. An exhaust fan is associated with the air exhaust opening so as to draw out air flowing from the second ventilation path through the air exhaust opening.Type: GrantFiled: March 22, 2006Date of Patent: February 13, 2007Assignee: Hitachi, Ltd.Inventors: Kenji Fuse, Mikio Shiraishi, Yasuo Otsuka, Nobuyuki Kaku, Hidehiro Ikeda