Abstract: According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.

Abstract: A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.

Abstract: According to one embodiment, a memory device is disclosed. The memory device includes a substrate, an on-volatile memory, a memory controller, an interconnect including one end and another end. The one end is connected to the memory controller. A footprint is on the substrate and connected to the another end of the interconnect. An ESD protection element is on the substrate and connected to the footprint. A connection terminal is on the substrate and connectable to a host device. A via plug is in the substrate. One end of the via plug is connected to the another end of the interconnect and another end of the first plug is connected to the connection terminal.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.

Abstract: A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.

Abstract: A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.

Abstract: A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.

Abstract: According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.

Abstract: According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.

Abstract: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.

Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.

Abstract: A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library including embedded circuit information, grasps physical positional relationships among elements such as terminals and wires, and checks whether the elements are short-circuited to each other or not. The library including embedded circuit information records a result of placement and routing output by the placement and routing processing unit, attribute information on a test circuit to be embedded into the customer circuit or terminal information and wire position information, and the like on the test circuit. The elements that are short-circuited to each other are incorporated into a netlist to be generated, as the elements constituting one net.

Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.

Abstract: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.

Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.

Abstract: The present invention discloses the structure of the array lens that at least any one of the diagonal size, vertical size and lateral size of lens cell is set to almost 1/(4.5 or more) for each corresponding size of the display elements, the structure that the diagonal size of lens cell is set to almost 0.18 inch or less, the structure that the total number of lens cells is set to almost 240 or more and the structure that the lens focal distance of lens cell is set to almost 30 mm or less.

Abstract: A projection type display apparatus includes a housing having a first side on which an air intake opening is arranged and a second side on which an air exhaust opening is arranged, a light source for supplying light, and a light valve device which modulates the light output from the light source. A first fan is provided which draws air from the air intake opening into the housing, and a first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve. A second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve, and a second fan is provided which draws out air flowing from the second ventilation path through the air exhaust opening to outside of the housing.

Abstract: A projection type display apparatus includes a housing having a first side having an air intake opening and a second side having an air exhaust opening, a light source for supplying light, and a light valve device which modulates the light output from the light source. A centrifugal fan is associated with the air intake opening so as to draw air from the air intake opening. A first ventilation path is coupled with the air intake opening so as to lead air flow from the air intake opening toward a lower portion of the light valve, and a second ventilation path is formed from the lower portion of the light valve to an upper portion of the light valve. An exhaust fan is associated with the air exhaust opening so as to draw out air flowing from the second ventilation path through the air exhaust opening.

Abstract: To reduce an influence on a customer circuit when a test circuit or the like is embedded into the customer circuit. Customer circuit design data 21 is the design data on the customer circuit targeted for design. A placement and routing processing unit 22 performs placement and routing processing on the customer circuit based on this design data. An embedded circuit generation processing unit 24 refers to a library including embedded circuit information 23, grasps physical positional relationships among elements such as terminals and wires, and checks whether the elements are short-circuited to each other or not. The library including embedded circuit information 23 records a result of placement and routing output by the placement and routing processing unit 22, attribute information on a test circuit to be embedded into the customer circuit or terminal information and wire position information, and the like on the test circuit.

Abstract: A liquid crystal projector comprises an illuminating optical system including a light source, a color separating optical system for separating illuminating light rays emitted by the illuminating optical system into light rays of three colors, a projection lens unit comprising a projection lens, a cross dichroic prism disposed near a light receiving end of the projection lens, and a plurality of liquid crystal panels arranged around the cross dichroic prism, and a light source power supply for supplying power to the light source. The projection lens unit, the color separating optical system, the illuminating optical system and the light source power supply are arranged in that order. The liquid crystal projector has an outside size in a horizontal plane of 263 mm by 318 mm or below. The liquid crystal panels have a display screen size of 0.9 in. A cooling fan for cooling the plurality of liquid crystal panels is disposed beside the projection lens.