Abstract: A semiconductor memory device comprises a plurality of memory cells having respective memory circuits for storing data bits each being of either logic "1" or logic "0" level in a rewritable manner, a read-out unit operative to selectively read out the data bits from the memory cells, a write-in unit operative to selectively write data bits into the memory cells, and a resetting unit operative to concurrently write reset data bits of a predetermined logic level into the memory cells, wherein the resetting unit comprises switching transistors respectively coupled to the memory circuits and a source of the predetermined logic level and is responsive to an external reset controlling signal for causing the switching transistors to concurrently turn on, thereby concurrently writing the reset data bits without failure.

Abstract: A static random access memory device has read-out bit lines for propagating read-out data bits to a selector circuit, and logic gates are coupled between the read-out bit lines and the selector circuit for inverting the data bits, wherein through current tends to flow through the logic gates due to decayed voltage levels on the read-out bit lines; however, only one of the logic gate coupled with a transfer transistor selected by a column address decoder is enabled so as to decrease the amount of the through current.