Patents by Inventor Yasuo Sugasawa

Yasuo Sugasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6249445
    Abstract: A booster is composed of a switching circuit outputting a clock signal and a charge pumping circuit boosting an input voltage to generate an output voltage in response to the clock signal. The switching circuit selects one from among frequencies as a frequency of the clock signal in response to the output voltage.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: June 19, 2001
    Assignee: NEC Corporation
    Inventor: Yasuo Sugasawa
  • Patent number: 5867046
    Abstract: A multi-phase clock generator for receiving an external clock signal through a PLL and for generating a plurality of internal clock signals differing in phase from each other. The multi-phase clock generator includes two large gates whose outputs are the two internal clock signals, and two latch circuits for controlling the logic gate outputs. The output from the PLL is fed forward to the logic gates so that the rise of one internal clock signal is separated from a prior fall of the other internal clock signal by a period related to the frequency of the PLL output.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: February 2, 1999
    Assignee: NEC Corporation
    Inventor: Yasuo Sugasawa