Abstract: A data processor of the present invention efficiently performs decision processing on register conflict. The data processor contains n-bit instructions and 2n-bit instructions in an instruction set and includes an instruction control unit that can decide whether registers specified in register specification fields of the instructions conflict between the instructions. The 2n-bit instructions including register specification fields have the register specification fields in the first half n bits thereof, and the register specification fields in the first half n bits comprise the same placement as register specification fields in the n-bit instructions. Shift operations required to cut out the register specification fields from the instructions, either 2n-bit or n-bit instructions, can be simplified or deleted by aligning the register specification fields in the 2n-bit instructions with those in the n-bit instructions.

Abstract: A data processor of the present invention reduces the program code size of a program for saving and restoring plural registers. The data processor includes a plurality of registers usable for instruction execution and has an instruction set including predetermined data transfer instructions. The predetermined data transfer instructions have register specification fields of plural bits in which the number of one register is explicitly specified from a group of registers, and specify data transfers between registers corresponding to numbers equal to or greater than, or equal to or smaller than a number specified in the register specification field and memory. A plurality of registers of the group of registers, specified in one operand, can be saved to and restored from memory. The program code size of a program for saving and restoring plural registers can be reduced. Since the predetermined instructions have only one operand, they can fit easily in 16 bits.