Abstract: A semiconductor memory device includes a plurality of main bit lines; a first bank including a plurality of memory cells, a plurality of word lines, and a plurality of sub bit lines; a second bank including a plurality of memory cells, a plurality of word lines, and a plurality of sub bit lines which are independent from the plurality of sub bit lines included in the first bank; a first auxiliary conduction region coupled to one of the plurality of main bit lines; a first switch for electrically connecting the first auxiliary conduction region to a second auxiliary conduction region: and a second switch for electrically connecting one of the plurality of sub bit lines included in the first bank to the second auxiliary conduction region.

Abstract: In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

Abstract: A plurality of memory cells of a semiconductor memory device of the present invention are classified into a plurality of column groups. Drain electrodes of the memory cells belonging to the same column group are connected to the same first bit line. Source electrodes of the memory cells belonging to the same column group are connected to the same second bit line. A gate electrode of the memory cell belonging to one of the column groups is connected to the gate electrode of the memory cell belonging to another one of the column groups via a word line. An amplifier amplifies a potential of the selected second bit line.

Abstract: In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.