Patents by Inventor Yasuo Taguchi

Yasuo Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934113
    Abstract: A developing cartridge may include: a casing; a developing roller extending in a first direction; a developing-roller gear; a coupling including a coupling gear; a first idle gear; a second idle gear; an agitator; a first agitator gear; and a protrusion. The developing-roller gear, the coupling, the first idle gear, the second idle gear, the first agitator gear, and the protrusion may be positioned at an outer surface of the casing. The protrusion may be positioned between a first axis of the coupling and a third axis of the first agitator gear in a second direction connecting the first and third axes. The protrusion may be positioned outside an addendum circle of the developing-roller gear, an addendum circle of the coupling gear, an addendum circle of the first idle gear, and an addendum circle of the second idle gear. The first agitator gear may be spaced apart from the protrusion in the first direction.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: March 19, 2024
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Yasuo Fukamachi, Kazuna Taguchi, Takuya Kanda
  • Publication number: 20060031655
    Abstract: The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.
    Type: Application
    Filed: October 5, 2005
    Publication date: February 9, 2006
    Inventors: Kei Kato, Masanao Yamaoka, Keiichi Higeta, Kazumasa Yanagisawa, Shigeru Shimada, Kodo Yamauchi, Yoshihiro Shinozaki, Yasuo Taguchi
  • Publication number: 20030145177
    Abstract: The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 31, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Kei Kato, Masanao Yamaoka, Keiichi Higeta, Kazumasa Yanagisawa, Shigeru Shimada, Kodo Yamauchi, Yoshihiro Shinozaki, Yasuo Taguchi
  • Patent number: 6163784
    Abstract: A method and an apparatus for controlling output of a document associated with a tab, bookmark or similar edge-projecting object outputs the document in its complete form including the projecting object. In one aspect, a position calculator routine is executed to calculate the amount of deviation between an expanded area of the document including the projecting object and an output area of the output apparatus, a document shift processor routine adjusts the location of the to align it with the output area of the output apparatus, and the apparatus outputs the document in its adjusted location. In another aspect, an area size calculator routine calculates physical dimensions of the expanded area of the document, a reduction processor calculates a reduction ratio based on physical dimensions of the output area of the apparatus and those of the expanded document area, and the apparatus outputs the document after reducing its size in accordance with the reduction ratio.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: December 19, 2000
    Assignee: Fuji Xerox Co., LTD
    Inventor: Yasuo Taguchi
  • Patent number: 6081817
    Abstract: A document edit system that performs page unit editing. The pages of a selected document are displayed in a stacked reduced offset overlapped position and are available for immediate editing independent of the page unit's location within the document stack. Display control data and actual data are stored for each page in internal memory and are changed in response to an edit command. Edit commands include page move and page copy within a single document, or from one document to another, and for creating a new document. The page move command may also be used to discard any selected page in the displayed document.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: June 27, 2000
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Yasuo Taguchi
  • Patent number: 5747887
    Abstract: The bus line of an electric power system is connected to an inverter which can be placed in a forward operation mode or in a reverse operation mode, and batteries are connected to the inverter to store the dc energy thereof. When a commercial power source is normal, an ac switch is closed, so that the inverter is placed in the forward operation mode to perform an active filter operation for eliminating harmonic current and reactive current. When necessary, the batteries are charged, and the inverter is placed in the reverse operation mode to perform a peak cut power generation. At loss of the commercial power source or momentary drop of the supply voltage, the switch is opened so that the inverter is placed in the reverse operation mode to perform an UPS operation (emergency power generation). Hence, electric power is supplied without interruption to an important load and the emergency load.
    Type: Grant
    Filed: March 17, 1993
    Date of Patent: May 5, 1998
    Assignees: Kundenko Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Toshiyuki Takanaga, Yasuo Taguchi, Seiji Sadayoshi, Mikio Kato, Kazuo Kuroki
  • Patent number: 4454560
    Abstract: An ignition detector circuit includes first and second resistors connected in series between a primary winding of a coil and the ground, a comparator having a first input terminal connected to the junction between first and second resistors and a second input terminal to which a reference voltage is applied, and a capacitor and a third resistor connected in parallel between the first input terminal of the comparator and the ground.
    Type: Grant
    Filed: November 9, 1981
    Date of Patent: June 12, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Satoshi Nakao, Yasuo Taguchi
  • Patent number: 4440130
    Abstract: An ignition control device includes a signal generating circuit for generating an output signal which has a frequency corresponding to the rotation speed of an engine, a rotation speed indication voltage generating circuit for generating a voltage which has a level corresponding to the rotation speed of engine, a saw-tooth wave generating circuit for generating a saw-tooth wave signal which changes at a frequency corresponding to the output signal from the signal generating circuit and at a rate corresponding to the voltage applied from the rotation speed indication voltage generating circuit, and a control circuit for generating an ignition signal every time when the saw-tooth wave signal has reached a predetermined voltage.
    Type: Grant
    Filed: July 14, 1981
    Date of Patent: April 3, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yasuo Taguchi, Satoshi Nakao
  • Patent number: 4424461
    Abstract: A semiconductor integrated circuit is temperature compensated by circuit elements which may be integrated on a typical semiconductor chip. The elements may include resistances formed by different means to have different temperature coefficients so that the collective temperature coefficient of the resistances can be adjusted by changing the values of the resistances.
    Type: Grant
    Filed: February 23, 1981
    Date of Patent: January 3, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yasuo Taguchi, Satoshi Nakao
  • Patent number: 4402299
    Abstract: An ignition coil energizing circuit is provided which has a signal generator for generating an output signal having a frequency corresponding to an engine rotational speed, a switching circuit connected to an ignition coil, a current detector for detecting a current flowing through the ignition coil, a duty control for supplying to the switching circuit a control signal having a duty cycle corresponding to a duty cycle of an output signal from the signal generator and controlling a conduction state of the switching circuit, and a current control circuit for controlling the switching circuit in response to an output signal generated from the current detector and maintaining a current flowing through the current detector at a predetermined value.
    Type: Grant
    Filed: October 6, 1981
    Date of Patent: September 6, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Satoshi Nakao, Yasuo Taguchi, Takashi Higuchi
  • Patent number: 4378779
    Abstract: An ignition system for an internal combustion engine includes two power transistors respectively connected to opposite ends of the primary winding of an ignition coil to interrupt the primary currents which flow from a power source through the mid-tap of the primary winding. The two power transistors have emitters connected in common and a resistor is connected to the junction of this common connection to detect respective primary currents with the single resistor. A single current control circuit is provided to control the two power transistors in response to the detected respective primary currents.
    Type: Grant
    Filed: July 28, 1980
    Date of Patent: April 5, 1983
    Assignees: Nippondenso Co., Ltd., Toshiba Corporation
    Inventors: Takasi Hachiga, Yasuo Taguchi
  • Patent number: 4191856
    Abstract: Disclosed is an analog multiplexer in which a plurality of emitter follower differential amplifiers formed of several pairs of bipolar transistors connected in parallel with each other are connected in common to one terminal of a power source through a current mirror load circuit, and to the other terminal of the power source via a switch circuit and a constant-current source. The switch circuit is to connect the constant-current source selectively to the common conjunction of the emitters of each pair of emitter follower differential amplifiers.
    Type: Grant
    Filed: July 28, 1978
    Date of Patent: March 4, 1980
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Katsumi Nagano, Yasuo Taguchi