Patents by Inventor Yasuo Tane
Yasuo Tane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9006029Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.Type: GrantFiled: March 21, 2011Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Patent number: 8772176Abstract: In a forming method of an adhesive layer including the steps of selectively coating, on a surface to be bonded, an adhesive composition containing a thermosetting composition and an organic solvent using a noncontact coating device; and removing the organic solvent from the adhesive composition coated on the surface to be bonded and in a forming method of an adhesive layer characterized in the thermosetting composition has a hardening property so as to exhibit two kinds of reaction temperatures, the adhesive composition comprising an epoxy resin and an epoxy curing agent which are reacted through a first hardening reaction exhibiting a first DSC peak within a temperature range of 100 to 160° C. and a second hardening reaction relating to a self-polymerization of the epoxy resin and exhibiting a second DSC peak within a temperature range of 140 to 200° C.Type: GrantFiled: March 15, 2011Date of Patent: July 8, 2014Assignees: Kyocera Chemical Corporation, Kabushiki Kaisha ToshibaInventors: Kazuyoshi Sakurai, Yuichi Noguchi, Norio Kurokawa, Yasuo Tane
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Patent number: 8691628Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.Type: GrantFiled: September 6, 2011Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami
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Patent number: 8629041Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.Type: GrantFiled: April 21, 2011Date of Patent: January 14, 2014Assignees: Kabushiki Kaisha Toshiba, KYOCERA Chemical CorporationInventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
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Publication number: 20120318431Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Patent number: 8276537Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: GrantFiled: January 18, 2011Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20120149151Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.Type: ApplicationFiled: September 6, 2011Publication date: June 14, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasuo TANE, Yukio KATAMURA, Atsushi YOSHIMURA, Fumihiro IWAMI
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Publication number: 20120052627Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.Type: ApplicationFiled: March 21, 2011Publication date: March 1, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20110267796Abstract: According to one embodiment, a semiconductor device includes a matrix and a semiconductor element bonded to the matrix via a bonding layer. The bonding layer includes a first layer and a second layer having a viscosity lower than a viscosity of the first layer at a bonding temperature. The first layer has a portion in which an end of the first layer is set further back to an inside than an end of the semiconductor element. At least a part of the portion set back to the inside is filled with a part of the second layer extruded from a periphery of the first layer to an outside.Type: ApplicationFiled: March 18, 2011Publication date: November 3, 2011Inventors: Atsushi YOSHIMURA, Yasuo Tane
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Publication number: 20110263078Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.Type: ApplicationFiled: April 21, 2011Publication date: October 27, 2011Applicants: KYOCERA CHEMICAL CORPORATION, Kabushiki Kaisha ToshibaInventors: Yasuo TANE, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
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Publication number: 20110263131Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.Type: ApplicationFiled: January 18, 2011Publication date: October 27, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
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Publication number: 20110263132Abstract: In a forming method of an adhesive layer including the steps of selectively coating, on a surface to be bonded, an adhesive composition containing a thermosetting composition and an organic solvent using a noncontact coating device; and removing the organic solvent from the adhesive composition coated on the surface to be bonded and in a forming method of an adhesive layer characterized in the thermosetting composition has a hardening property so as to exhibit two kinds of reaction temperatures, the adhesive composition comprising an epoxy resin and an epoxy curing agent which are reacted through a first hardening reaction exhibiting a first DSC peak within a temperature range of 100 to 160° C. and a second hardening reaction relating to a self-polymerization of the epoxy resin and exhibiting a second DSC peak within a temperature range of 140 to 200° C.Type: ApplicationFiled: March 15, 2011Publication date: October 27, 2011Applicants: KABUSHIKI KAISHA TOSHIBA, KYOCERA CHEMICAL CORPORATIONInventors: Kazuyoshi Sakurai, Yuichi Noguchi, Norio Kurokawa, Yasuo Tane
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Publication number: 20110263097Abstract: According to one embodiment, a method for manufacturing semiconductor device can include forming a groove with a depth shallower than a thickness of a wafer. The method can include attaching a surface protection tape via a first bonding layer provided in the surface protection tape. The method can include grinding a surface of the wafer to divide the wafer into a plurality of semiconductor elements. The method can include forming an element bonding layer by attaching a bonding agent and turning the attached bonding agent into a B-stage state. The method can include attaching a dicing tape via a second bonding layer provided in the dicing tape. The method can include irradiating the first bonding layer with a first active energy ray. The method can include removing the surface protection tape. The method can include irradiating the second bonding layer with a second active energy ray.Type: ApplicationFiled: March 22, 2011Publication date: October 27, 2011Inventors: Atsushi YOSHIMURA, Yasuo TANE, Yukio KATAMURA, Fumihiro IWAMI
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Publication number: 20110263133Abstract: A semiconductor device manufacturing apparatus includes: an accommodation section accommodating an application object; an irradiation section irradiating the application object taken out from the accommodation section with ultraviolet light; an application section including a stage allowing the application object to be placed thereon and an application head discharging a plurality of droplets of an adhesive to the application object placed on the stage, the application section applying the adhesive through the application head to the application object which is irradiated by ultraviolet light through the irradiation section and is placed on the stage; a drying section drying the adhesive applied on the application object with heat; and a transport section including a hand supporting the application object, the transport section which is capable of transporting the application object accommodated in the accommodation section to the irradiation section, the application section, and the drying section.Type: ApplicationFiled: April 22, 2011Publication date: October 27, 2011Applicants: Kabushiki Kaisha Toshiba, SHIBAURA MECHATRONICS CORPORATIONInventors: Satoru Hara, Shingo Tamai, Akihiro Shigeyama, Michio Ogawa, Hitoshi Aoyagi, Hiroyuki Tanaka, Yasuo Tane, Yukio Katamura
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Publication number: 20070196952Abstract: A substrate having an element mounting portion is placed on a suction stage having a suction hole. The suction hole is provided so as to suck a region excluding the element mounting portion of the substrate. Otherwise, the suction hole has a hole size of not less than 0.5 mm nor more than 1.0 mm. A fist semiconduct or substrate is sucked with a suction rubber collet with Shore A hardness of not less than 50 nor more than 70. The first semiconductor element is bonded to the element mounting portion of the substrate. A second semiconductor element having an adhesive layer with a remaining volatile content of 0.5% or less is disposed on the first semiconductor substrate. The adhesive layer is heated to a temperature in a range of not less than 120° C. nor more than 150° C. and bonded.Type: ApplicationFiled: January 10, 2007Publication date: August 23, 2007Inventors: Atsushi Yoshimura, Tadanobu Okubo, Yasuo Tane
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Patent number: 6208019Abstract: A card-type semiconductor device including a thin (e.g., 30 to 70 &mgr;m) semiconductor chip which is thinner than an insulating resin film embedded in a device hole of a wiring film. The wiring film includes a copper wiring layer and inner leads arranged on one main face of the insulating resin film. Electrode pads are bonded to the inner leads by heating and pressing. A sealing resin layer is formed on the exterior of the bonded portion as required, and a polyester resin film is integrally laminated on the upper and lower faces of the wiring film. The card-type semiconductor device with the above construction has sufficient strength against bending, etc., and is suitable for integrated circuit (IC) card applications.Type: GrantFiled: March 10, 1999Date of Patent: March 27, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Tane, Kazuyasu Tanaka
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Patent number: 5528077Abstract: A TAB semiconductor device according to the present invention is as follows. One end of each lead whose direction is fixed by a TAB tape is connected to a corresponding electrode on a semiconductor pellet placed at a predetermined position of the TAB tape. The TAB tape is a tape having the thin leads fixed on a film and a portion where the film is removed, i.e., a window portion in a predetermined area. Only the arrangement of the leads is exposed to the window portion. A user arbitrarily cuts the leads in this area in accordance with mounting. The leads have normal signal leads and wider leads together. As for these wider leads, slits are provided to make the lead widths uniform throughout the window portion.Type: GrantFiled: March 6, 1995Date of Patent: June 18, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Tane, Jiro Nakano, Jun-ichi Ohno
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Patent number: 5442241Abstract: A semiconductor device comprising a semiconductor substrate having an insulating film thereon, a pad electrode provided on the insulating film, first and second bumps disposed on the pad electrode to provide a gap therebetween, and a lead wire coupled to the gap. In the structure, each of the first and second bumps has a straight or mushroom bump structure.Type: GrantFiled: July 22, 1994Date of Patent: August 15, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Yasuo Tane