Patents by Inventor Yasuo Tarui

Yasuo Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6885048
    Abstract: A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: April 26, 2005
    Assignees: Nippon Precision Circuits Inc.
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Patent number: 6750501
    Abstract: A ferroelectric body transistor having a structure of MFMIS (conductor film) -ferroelectric film-conductor film-insulating film-semiconductor) including a gate insulator capacitor having an MIS structure, a low dielectric constant layer restraining layer interposed between an insulating film made of a material having a high inductive capacity of CeO2 and a semiconductor substrate to thereby restrain a low dielectric constant layer of SiO2 or the like from being produced at an interface between the insulating film and the semiconductor substrate and restrain a capacitance from being reduced. An area of the gate insulator capacitor can be reduced and highly integrated formation is provided.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: June 15, 2004
    Assignees: Nippon Precision Circuits Inc.
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Publication number: 20040042290
    Abstract: A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIM (metal-insulator-metal) structure.
    Type: Application
    Filed: March 8, 2001
    Publication date: March 4, 2004
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Patent number: 6608339
    Abstract: Ferroelectric memory element having an MFIS structure including a silicon semiconductor substrate and an insulating film arranged above the silicon semiconductor substrate. The insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film so that an unnecessary, low dielectric constant layer is prevented from forming between the semiconductor substrate and the insulating film. A ferroelectric film is arranged on the insulating film. The low dielectric constant layer restraining film is thinner than the ferroelectric film.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: August 19, 2003
    Assignees: Yasuo Tarui, Nippon Precision Circuits Inc.
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Publication number: 20020149042
    Abstract: To progress highly integrated formation and promote reliability in a ferroelectric body transistor having a structure of MFMIS (conductor film-ferroelectric film-conductor film-insulating film-semiconductor), in a gate insulator capacitor comprising an MIS structure, a low dielectric constant layer restraining layer 2 is interposed between an insulating film 3 comprising a material having a high inductive capacity of CeO2 and a semiconductor substrate 1 to thereby restrain a low dielectric constant layer of SiO2 or the like from being produced at an interface between the insulating film 3 and the semiconductor substrate 1 and restrain a capacitance from being reduced. An area of the gate insulator capacitor can be reduced and highly integrated formation is progressed.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 17, 2002
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Publication number: 20010028582
    Abstract: To resolve a problem that in a ferroelectric memory element having MFIS (metal—ferroelectric material—insulating material—semiconductor) structure, in forming an insulating film (buffer layer) and a ferroelectric thin film, unnecessary low dielectric constant layer is formed between a silicon semiconductor substrate and the insulating film (buffer layer) by which capacitance of the insulating film is lowered and voltage sufficient for inversion of polarization of the ferroelectric material cannot be applied, there is provided a ferroelectric memory element of MFIS structure in which an insulating film (2) above a silicon semiconductor substrate (1) includes a low dielectric constant layer restraining film (3) and a mutual diffusion preventive film (4) and unnecessary low dielectric constant layer is restrained from forming between the semiconductor substrate and the insulating film.
    Type: Application
    Filed: April 2, 2001
    Publication date: October 11, 2001
    Inventors: Yasuo Tarui, Kazuo Sakamaki
  • Patent number: 6084260
    Abstract: An Si oxide film, an oriented paraelectric oxide thin film and an oriented ferroelectric thin film are laminated on an Si single crystal substrate having a region for a source and a drain. A conductor thin film is formed in a portion not covered with an insulating film. A laminated structure formed of the Si oxide film, the oriented paraelectric oxide thin film and the oriented ferroelectric thin film is used as a gate of a transistor. The Si oxide film functions as a carrier injection inhibiting layer.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: July 4, 2000
    Assignees: Asahi Kasei Kogyo Kabushiki Kaisha, Yasuo Tarui
    Inventors: Tadahiko Hirai, Yasuo Tarui
  • Patent number: 5955755
    Abstract: An Si oxide film, an oriented paraelectric oxide thin film and an oriented ferroelectric thin film are laminated on an Si single crystal substrate having a region for a source and a drain. A conductor thin film is formed in a portion not covered with an insulating film. A laminated structure formed of the Si oxide film, the oriented paraelectric oxide thin film and the oriented ferroelectric thin film is used as a gate of a transistor. The Si oxide film functions as a carrier injection inhibiting layer.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: September 21, 1999
    Assignees: Asahi Kasei Kogyo Kabushiki Kaisha, Yasuo Tarui
    Inventors: Tadahiko Hirai, Yasuo Tarui
  • Patent number: 5674563
    Abstract: A ferroelectric thin film is produced on a substrate placed in an oxygen gas atmosphere within a reaction chamber. Evaporated source materials (organic metal compounds) are separately introduced in a predetermined sequence into the reaction chamber to produce a PZT or PLZT layer structure having an estimated stoichiometric composition. This cycle of introduction of the source materials is repeated continuously to produce a PZT or PLZT ferroelectric thin film having a predetermined number of PZT or PLZT layer structures piled on the substrate.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: October 7, 1997
    Assignees: Nissan Motor Co., Ltd., Sharp Kabushiki Kaisha, Yasuo Tarui
    Inventors: Yasuo Tarui, Yoshihiro Soutome, Shinichi Morita, Satoshi Tanimoto
  • Patent number: 4046594
    Abstract: Disclosed is a solar battery comprising a multi-layered "p-n" junction structure, which has a plurality of inwardly converging recesses to partially expose the inner "p-n" junctions to the sun light.
    Type: Grant
    Filed: March 26, 1976
    Date of Patent: September 6, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Yasuo Tarui, Tsunenori Sakamoto, Yoshio Komiya
  • Patent number: 4015283
    Abstract: In an element of an integrated circuit including a transistor and a "majority carrier diode" at least one terminal of which is connected to the base or collector of said transistor, the "majority carrier diode" is laid out in a transistor portion of the integrated circuit to be surrounded by a part of base region extended to the surface of the semiconductor body, so that the paths for the load current of the transistor and the diode current are separated from each other, whereby a high speed operation at a heavy load current is made possible and/or so that reliability of said majority carrier diode is increased.
    Type: Grant
    Filed: July 25, 1975
    Date of Patent: March 29, 1977
    Assignee: Kogyo Gijutsuin
    Inventors: Yutaka Hayashi, Yasuo Tarui
  • Patent number: 4003632
    Abstract: Disclosed is an optoelectronic semiconductor comprising a semiconductor substrate, a first insulating film covering the major surface of the semiconductor substrate and a second insulating film having electronic charge-storing means and lying on the first insulating film. When an optically guided wave is propagated to the first or second insulating film in the direction parallel to the major surface of the semiconductor substrate, an interaction is caused between the electronic charges stored in the charge-storing means and the optically guided wave, thereby allowing the optically guided wave to be modulated and the electronic charges to be released.
    Type: Grant
    Filed: March 26, 1975
    Date of Patent: January 18, 1977
    Assignee: Agency of Industrial Science & Technology
    Inventors: Yoshio Komiya, Eiichi Suzuki, Yasuo Tarui
  • Patent number: 3950738
    Abstract: A semiconductor non-volatile optical memory device is constructed by providing light-permeable charge retention means in an insulating layer on a first semiconductor surface into which photo-generated carriers in the surface of the first semiconductor region are injected over the semiconductor-insulator potential barrier by applying reverse bias between the first semiconductor region and a second region forming a rectifying junction with the first semiconductor region. Also disclosed in a non-volatile memory integrated circuit employing one or more of said devices together with light source in the same package. The non-volatile memory integrated circuit operates under low bias voltage and is compatible with a high speed integrated logic circuits.
    Type: Grant
    Filed: July 12, 1974
    Date of Patent: April 13, 1976
    Assignee: Agency of Industrial Science & Technology
    Inventors: Yutaka Hayashi, Kiyoko Nagai, Yasuo Tarui
  • Patent number: 3950777
    Abstract: Disclosed herein is an improved field-effect transistor, having its effective base width determined by the impurity diffusion length or by a difference between impurity diffusion lengths for providing a reduced parasitic capacitance between gate and drain, and/or between gate or drain and other electrode. Disclosed also is a construction for effectively leading out an electrode from the base region and or source region, and methods adapted to manufacture the above-mentioned field-effect transistor.
    Type: Grant
    Filed: March 15, 1973
    Date of Patent: April 13, 1976
    Assignee: Kogyo Gijutsuin
    Inventors: Yasuo Tarui, Yutaka Hayashi, Toshihiro Sekigawa
  • Patent number: 3946424
    Abstract: A high frequency insulated gate field effect transistor comprises a semiconductor body of one type of conductivity, a base region of the same type of conductivity as the semiconductor body but with a higher impurity concentration than the body, and drain and source regions of the opposite type of conductivity. A portion of the base region is disposed between the drain region and the source region and the impurity concentration of the base region is reduced from the source region toward the drain region and is less at its junction with the drain region than that of the drain region. Such transistor can be incorporated in an integrated circuit as an amplifier transistor with a depletion type transistor as a load transistor. A common region serves both as a drain region of the amplifier transistor and a source region of the load transistor.
    Type: Grant
    Filed: August 13, 1974
    Date of Patent: March 23, 1976
    Assignee: Kogyo Gijutsuin
    Inventors: Yasuo Tarui, Yutaka Hayashi