Patents by Inventor Yasuo TERUI

Yasuo TERUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9694523
    Abstract: A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip includes upper and lower molds configured to receive therebetween a lead frame on which the semiconductor chip is mounted. A positioning pin provided to the lower mold is configured to be received by a positioning hole provided in the lead frame. Ejector pins provided in proximity to the positioning pin are arranged so as to be symmetrical with respect to the positioning pin.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 4, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Yasuo Terui, Masaru Akino
  • Publication number: 20160176088
    Abstract: A lower mold (2) of a set of upper and lower molds for resin encapsulation of a lead frame having a semiconductor chip mounted thereon is provided with a tapered positioning pin (3) to be engaged with a positioning hole formed in the lead frame. A columnar portion of the tapered positioning pin has an outer diameter larger than an inner diameter of a positioning hole. An ejector pin (4) and an ejector pin in a pair (5) for ejecting a package out of the molds after the molding are fixed to an ejector pin coupling mechanism (6).
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventors: Yasuo TERUI, Masaru AKINO
  • Patent number: 9296142
    Abstract: A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip. A lead frame on which the semiconductor chip is mounted is provided between an upper mold and a lower mold. A tapered positioning pin is provided to the lower mold and includes a columnar portion having an outer diameter larger than an inner diameter of a positioning hole provided at an upper surface of the lead frame and configured to receive the columnar portion of the tapered positioning pin. Ejector pins are disposed in proximity to the tapered positioning pin at a distance determined by a thickness of the lead frame. The ejector pins are arranged so as to be symmetrical with respect to the tapered positioning pin.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 29, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Yasuo Terui, Masaru Akino
  • Publication number: 20150086666
    Abstract: A lower mold (2) of a set of upper and lower molds for resin encapsulation of a lead frame having a semiconductor chip mounted thereon is provided with a tapered positioning pin (3) to be engaged with a positioning hole formed in the lead frame. A columnar portion of the tapered positioning pin has an outer diameter larger than an inner diameter of a positioning hole. An ejector pin (4) and an ejector pin in a pair (5) for ejecting a package out of the molds after the molding are fixed town ejector pin coupling mechanism (6).
    Type: Application
    Filed: September 24, 2014
    Publication date: March 26, 2015
    Inventors: Yasuo TERUI, Masaru AKINO