Abstract: Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: The invention relates to an arrangement for testing and repairing an inteted circuit in which the ion beam used for the repair simultaneously forms the corpuscular beam used for the test operation and one single beam generator is provided in order to generate this beam. Testing and repairing in one arrangement, without it being necessary to transfer the integrated circuit to be examined, reduces the expenditure in terms of time and cost.

Abstract: An automobile rear window structure for closing a rear window opening formed in an automobile body, the opening having front and rear edges and opposite sides. The window closing structure includes a pair of rear pillars extending along both sides of the rear window opening and having trough sections formed therein. Transparent material closing the rear opening includes a rear section and a pair of side sections positioned on opposite sides of the rear section. The side sections have transverse curvatures which are contiguous with a transverse curvature of the rear section. The rear section is formed separately from the side sections and is arranged to cover the rear window opening and has an upper end hinged to the body for swinging movement between closed and open positions.