Patents by Inventor Yasuo Ueda
Yasuo Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200007700Abstract: There is provided an information processing device comprising a memory and a processor coupled to the memory and the processor configured to: write channel specifying information for specifying a channel used for radio connection, into the memory; and attempt to establish a radio connection during activation of a radio connection function, by using channel specifying information on a channel used for a last radio connection, out of the channel specifying information written into the memory, wherein the memory is a non-volatile memory, and the processor is further configured to write only channel specifying information on the currently employed channel into the non-volatile memory when the information processing device is instructed to disconnect a power supply.Type: ApplicationFiled: September 27, 2018Publication date: January 2, 2020Inventors: Osamu MIYAKAWA, Hitoshi MATSUO, Yasuo UEDA
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Publication number: 20160357470Abstract: A method includes: allocating a first divided region in a user space to a program executed in a user mode, the first divided region being one of a plurality of divided regions obtained by dividing a storing region of a memory, storing information which indicates that the data to be stored is confidential, in association with the first divided region allocated to the program; storing, when data stored in the first divided region is copied to a second divided region in a kernel space among the plurality of divided regions of the storing region and when the information is associated with the first divided region, the information in association with the second divided region; and dumping, when the second divided region with which the information is associated is included in a dump target, encryption data which is obtained by encrypting the data stored in the second divided region.Type: ApplicationFiled: May 27, 2016Publication date: December 8, 2016Applicant: FUJITSU LIMITEDInventors: Naotaka Hamaguchi, Yasuo Ueda, Toshiyuki Okajima, Nobuyuki Akiyama, Hidetoshi Seto, Hideo Shitaya, Hiroyuki Kamezawa
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Patent number: 9507724Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.Type: GrantFiled: August 3, 2015Date of Patent: November 29, 2016Assignee: FUJITSU LIMITEDInventors: Hiroyuki Kamezawa, Yasuo Ueda, Tsutomu Itoh, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto
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Patent number: 9507657Abstract: A non-transitory computer readable storage medium that stores therein an investigation program for causing an information processing apparatus to execute processing, the processing includes creating, in a storage medium, a first dump file for writing out data in a memory in the information processing apparatus when an operating system detects a first abnormality, rebooting the information processing apparatus without erasing the data stored in the memory after the detection of the first abnormality and after the creation of the first dump file, creating, during the reboot, a first table that associates a plurality of page areas in the memory and a plurality of dump file areas in the first dump file that correspond to the page areas, and writing out, when a page area in the memory is released, data stored in the page area to the first dump file.Type: GrantFiled: November 25, 2014Date of Patent: November 29, 2016Assignee: FUJITSU LIMITEDInventors: Hideyuki Niwa, Hiroyuki Kamezawa, Yasuo Ueda, Yuichi Nagahama, Hidetoshi Seto, Taku Izumi, Yasuaki Ishimatsu, Ken Ichikawa
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Patent number: 9491357Abstract: An image-processing system includes a receiver which receives an input value defining an output range, a generator which generates a three-dimensional model having a target image attached to a three-dimensional conformation, a decision part which decides a position of a viewing point and a viewing angle in accordance with the input value, and a projector which projects the three-dimensional model from the viewing point, wherein the decision part changes a range of a target image inside a viewing field by changing the viewing angle preferentially when the input value is in a first range, and changes the range of the target image inside the viewing field by changing the viewing point preferentially when the input value is in a second range which is a wider-angle side than that of the first range.Type: GrantFiled: October 23, 2014Date of Patent: November 8, 2016Assignee: RICOH COMPANY LTD.Inventors: Makoto Shohara, Nozomi Imae, Toru Harada, Hideaki Yamamoto, Yasuo Ueda, Yoichi Ito, Satoshi Sawaguchi, Hirokazu Takenaka, Kensuke Masuda, Hiroyuki Satoh
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Patent number: 9442790Abstract: A circuitry of a computer is configured to monitor an update state in a prescribed period of time of a plurality of units of management of data stored in the memory device for each of the plurality of units, to select a target unit as a target of dumping that outputs data from among the plurality of units on the basis of a monitoring result of the update state, and to dump data corresponding to the selected target unit.Type: GrantFiled: July 11, 2014Date of Patent: September 13, 2016Assignee: FUJITSU LIMITEDInventors: Yuichi Nagahama, Hidetoshi Seto, Yasuo Ueda, Hideyuki Niwa, Yasuaki Ishimatsu, Taku Izumi, Hiroyuki Kamezawa, Kenji Kaneshige, Ken Ichikawa
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Patent number: 9392167Abstract: An image-processing system includes a receiver which receives an input value defining an output range, a generator which generates a three-dimensional model having a target image attached to a three-dimensional conformation, a decision part which decides a position of a viewing point and a viewing angle in accordance with the input value, and a projector which projects the three-dimensional model from the viewing point, wherein the decision part changes a range of a target image inside a viewing field by changing the viewing angle preferentially when the input value is in a first range, and changes the range of the target image inside the viewing field by changing the viewing point preferentially when the input value is in a second range which is a wider-angle side than that of the first range.Type: GrantFiled: December 12, 2013Date of Patent: July 12, 2016Assignee: RICOH COMPANY, LTD.Inventors: Makoto Shohara, Nozomi Imae, Toru Harada, Hideaki Yamamoto, Yasuo Ueda, Yoichi Ito, Satoshi Sawaguchi, Hirokazu Takenaka, Kensuke Masuda, Hiroyuki Satoh
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Publication number: 20160062902Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.Type: ApplicationFiled: August 3, 2015Publication date: March 3, 2016Inventors: Hiroyuki KAMEZAWA, Yasuo UEDA, TSUTOMU ITOH, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto
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Patent number: 9195548Abstract: A disclosed information processing method is executed by a computer and includes: storing context representing a state of a processor in the computer into a certain area of plural areas included in a memory of the computer, wherein same data is stored in each of the plural areas by memory mirroring; performing a setting to switch a type of the certain area from a type of an area for which the memory mirroring is performed to a type of an area for securing data; and upon detecting that reset of the computer was performed, recovering, by using the computer, the state of the processor by using data stored in the certain area.Type: GrantFiled: May 21, 2013Date of Patent: November 24, 2015Assignee: FUJITSU LIMITEDInventors: Hideyuki Niwa, Yasuo Ueda
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Publication number: 20150160994Abstract: A non-transitory computer readable storage medium that stores therein an investigation program for causing an information processing apparatus to execute processing, the processing includes creating, in a storage medium, a first dump file for writing out data in a memory in the information processing apparatus when an operating system detects a first abnormality, rebooting the information processing apparatus without erasing the data stored in the memory after the detection of the first abnormality and after the creation of the first dump file, creating, during the reboot, a first table that associates a plurality of page areas in the memory and a plurality of dump file areas in the first dump file that correspond to the page areas, and writing out, when a page area in the memory is released, data stored in the page area to the first dump file.Type: ApplicationFiled: November 25, 2014Publication date: June 11, 2015Inventors: Hideyuki Niwa, Hiroyuki KAMEZAWA, Yasuo UEDA, Yuichi Nagahama, Hidetoshi Seto, TAKU IZUMI, Yasuaki Ishimatsu, Ken Ichikawa
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Publication number: 20150046754Abstract: A circuitry of a computer is configured to monitor an update state in a prescribed period of time of a plurality of units of management of data stored in the memory device for each of the plurality of units, to select a target unit as a target of dumping that outputs data from among the plurality of units on the basis of a monitoring result of the update state, and to dump data corresponding to the selected target unit.Type: ApplicationFiled: July 11, 2014Publication date: February 12, 2015Inventors: Yuichi Nagahama, Hidetoshi Seto, Yasuo UEDA, Hideyuki Niwa, Yasuaki Ishimatsu, TAKU IZUMI, Hiroyuki KAMEZAWA, Kenji Kaneshige, Ken Ichikawa
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Publication number: 20150042647Abstract: An image-processing system includes a receiver which receives an input value defining an output range, a generator which generates a three-dimensional model having a target image attached to a three-dimensional conformation, a decision part which decides a position of a viewing point and a viewing angle in accordance with the input value, and a projector which projects the three-dimensional model from the viewing point, wherein the decision part changes a range of a target image inside a viewing field by changing the viewing angle preferentially when the input value is in a first range, and changes the range of the target image inside the viewing field by changing the viewing point preferentially when the input value is in a second range which is a wider-angle side than that of the first range.Type: ApplicationFiled: October 23, 2014Publication date: February 12, 2015Inventors: Makoto SHOHARA, Nozomi Imae, Toru Harada, Hideaki Yamamoto, Yasuo Ueda, Yoichi Ito, Satoshi Sawaguchi, Hirokazu Takenaka, Kensuke Masuda, Hiroyuki Satoh
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Publication number: 20140189422Abstract: An information processing apparatus includes: a dividing unit that divides a storage region in accordance with storage region management information, the storage region management information and type information; a setting unit that selects a first division region from division regions indicative of the divided storage region and that puts the first division region in a stand-by state; a detecting unit that detects an abnormality in information processing when the information processing is performed using a second division region of the division regions; a controlling unit that puts the second division region in the stand-by state and that causes the first division region, which has been in the stand-by state, to recover; and an analyzing unit that adds the second division region that is in the stand-by state to a physical address space, and that analyzes information stored in the second division region.Type: ApplicationFiled: December 11, 2013Publication date: July 3, 2014Applicant: FUJITSU LIMITEDInventors: Hideyuki NIWA, Yasuo UEDA
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Publication number: 20140176542Abstract: An image-processing system includes a receiver which receives an input value defining an output range, a generator which generates a three-dimensional model having a target image attached to a three-dimensional conformation, a decision part which decides a position of a viewing point and a viewing angle in accordance with the input value, and a projector which projects the three-dimensional model from the viewing point, wherein the decision part changes a range of a target image inside a viewing field by changing the viewing angle preferentially when the input value is in a first range, and changes the range of the target image inside the viewing field by changing the viewing point preferentially when the input value is in a second range which is a wider-angle side than that of the first range.Type: ApplicationFiled: December 12, 2013Publication date: June 26, 2014Inventors: Makoto Shohara, Nozomi Imae, Toru Harada, Hideaki Yamamoto, Yasuo Ueda, Yoichi Ito, Satoshi Sawaguchi, Hirokazu Takenaka, Kensuke Masuda, Hiroyuki Satoh
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Patent number: 8665003Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.Type: GrantFiled: September 3, 2010Date of Patent: March 4, 2014Assignee: Ricoh Company, Ltd.Inventors: Yasuo Ueda, Masashi Tokuda, Toshihiro Tsukagoshi
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Publication number: 20140006855Abstract: A disclosed information processing method is executed by a computer and includes: storing context representing a state of a processor in the computer into a certain area of plural areas included in a memory of the computer, wherein same data is stored in each of the plural areas by memory mirroring; performing a setting to switch a type of the certain area from a type of an area for which the memory mirroring is performed to a type of an area for securing data; and upon detecting that reset of the computer was performed, recovering, by using the computer, the state of the processor by using data stored in the certain area.Type: ApplicationFiled: May 21, 2013Publication date: January 2, 2014Applicant: FUJITSU LIMITEDInventors: Hideyuki NIWA, Yasuo Ueda
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Patent number: 8395457Abstract: A triangular wave generator in a pulse width modulation signal generator to generate a triangular wave signal and a pair of pulse signals. The first pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a minimum limit thereof. The second pulse signal is pulsed for a given duration of time when the triangular wave signal reaches a maximum limit thereof. The voltage comparator generates a first pulse width modulation signal by comparing the triangular wave signal with an externally supplied direct current signal. The wave shaping circuit generates a second pulse width modulation signal by removing chattering components occurring immediately after rising and falling edges of the first pulse width modulation signal with a masking signal generated based on the first and second pulse signals and the first pulse width modulation signal.Type: GrantFiled: March 9, 2011Date of Patent: March 12, 2013Assignee: Ricoh Company, Ltd.Inventor: Yasuo Ueda
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Patent number: 8382343Abstract: In an electronic device including a temperature sensor and an electronic component which is a heat generation source, the temperature is measured while the influence of heat from the electronic component is reduced. The electronic device includes: a base formed of a resin material; a board which is disposed at one side of the base, and includes an electronic component and a temperature sensor; and a heat sink which is disposed at the other side of the base for dissipating heat generated by the electronic component. The heat sink includes an extension part extending from the other side of the base toward a position of the board at which the electronic component is provided.Type: GrantFiled: December 6, 2010Date of Patent: February 26, 2013Assignee: Panasonic CorporationInventors: Noriaki Terahara, Seiji Hoshi, Yoshiyuki Hashimoto, Takeshi Ohta, Toshiyasu Tanaka, Yasuo Ueda, Toshiaki Takasu
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Patent number: 8269527Abstract: A hysteresis comparator circuit that compares first and second input signals to output a hysteresis output signal includes a constant current source, a first comparator, a second comparator, and an output circuit. The constant current source includes a load resistor to generate a given constant current. The first comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a first comparison result. The second comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a second comparison result. The output circuit has a pair of inputs thereof connected to the first and second comparators, respectively, which inverts an output thereof in response to each of the first and second comparison results to generate the hysteresis output signal.Type: GrantFiled: September 2, 2010Date of Patent: September 18, 2012Assignee: Ricoh Company, Ltd.Inventor: Yasuo Ueda
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Publication number: 20120126735Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.Type: ApplicationFiled: September 3, 2010Publication date: May 24, 2012Inventors: Yasuo Ueda, Masashi Tokuda, Toshihiro Tsukagoshi