Patents by Inventor Yasuo Yamagishi

Yasuo Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160066421
    Abstract: A solder paste includes: solder particles containing Sn and Bi; an epoxy resin having two or more epoxy groups; an epoxy compound having one epoxy group; and a curing agent. And an electronic part includes: a wiring board provided with an electrode pad; a part mounted on the wiring board and provided with a plurality of electrodes; and a cured product of a solder paste configured to connect the plurality of electrodes and the electrode pad, wherein the solder paste includes: solder particles containing Sn and Bi; an epoxy resin having two or more epoxy groups; an epoxy compound having one epoxy group; and a curing agent.
    Type: Application
    Filed: August 21, 2015
    Publication date: March 3, 2016
    Applicant: Fujitsu Limited
    Inventors: Kazuhiro Kitamura, Tomohisa YAGI, HIROAKI DATE, Yasuo Yamagishi
  • Patent number: 7678695
    Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Limited
    Inventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
  • Patent number: 7595228
    Abstract: A method for manufacturing an electronic component-mounted board (X) includes a temperature raising step for heating an electronic component (30A), with a solder bump electrode (31) containing a solder material, to a first temperature higher than the melting point of the solder material, while also heating a wiring board (X?), with an electrode section (21) corresponding to the solder bump electrode (31), to a second temperature lower than the first temperature. The method further includes a joining step for joining the solder bump electrode (31) and the electrode section (21) by pressing the electronic component (30A) against the wiring board (X?), with the solder bump electrodes (31) and the electrode sections (21) abutting against each other.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: September 29, 2009
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Yasuo Yamagishi
  • Patent number: 7557014
    Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: July 7, 2009
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
  • Patent number: 7449900
    Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 11, 2008
    Assignee: Fujitsu Limited
    Inventor: Yasuo Yamagishi
  • Patent number: 7359594
    Abstract: An optical waveguide structure capable of optically coupling a surface type optical device, such as a surface emitting laser diode or a photodiode, and a transmission medium, such as an optical fiber, located so that their light output surface and light input surface will form an angle of about 90° with each other simply and easily. The optical waveguide structure comprises a first clad section having a curved surface for gradually turning the direction in which light travels almost squarely and a groove formed in the curved surface along the direction in which light travels, a core section which is made from a transparent material with a refractive index higher than the refractive index of the first clad section and with which the groove is filled in, and a second clad section which covers an exposed surface of the core section and the curved surface of the first clad section and which is integrated with the first clad section.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: April 15, 2008
    Assignee: Fujitsu Limited
    Inventors: Motoyuki Nishizawa, Koji Tsukamoto, Masayuki Kato, Yasuo Yamagishi
  • Patent number: 7351361
    Abstract: A conductive composition layer, conductive particles as a raw material, a conductive composition therefor, a manufacturing method of the conductive composition layer, etc. are provided wherewith heat conductance can be accelerated between electronic devices or electronic devices can be electrically connected. The conductive composition layer is formed by subjecting to heat treatment at a temperature lower than 230° C. a conductive composition comprising conductive particles having a metal base material and a metal coating material thereon as well as a thermosetting resin having a curing temperature that is lower than 230° C. and/or a thermoplastic resin having a melting point that is lower than 230° C.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: April 1, 2008
    Assignee: Fujitsu Limited
    Inventors: Kozo Shimizu, Yasuo Yamagishi
  • Publication number: 20070155174
    Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.
    Type: Application
    Filed: March 7, 2007
    Publication date: July 5, 2007
    Applicant: FIJITSU LIMITED
    Inventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
  • Patent number: 7211899
    Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: May 1, 2007
    Assignee: Fujitsu Limited
    Inventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
  • Publication number: 20070065981
    Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.
    Type: Application
    Filed: November 16, 2006
    Publication date: March 22, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
  • Patent number: 7176556
    Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: February 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Keishiro Okamoto, Takeshi Shioga, Osamu Taniguchi, Koji Omote, Yoshihiko Imanaka, Yasuo Yamagishi
  • Patent number: 7149372
    Abstract: The optical device comprises a first substrate 10 having a control circuit formed on; optical waveguide layer 40 formed above the first substrate and having a refractive index changed by electro-optic effect; and second substrates 14a, 14b having prism electrodes 18 for applying voltages to the optical waveguide layer. The control circuit and the prism electrodes are electrically connected to each other via columnar conductors 20. Even in a case where thermal expansion coefficients of the control substrate and of the light deflection substrates are very different from each other, the pins are flexed corresponding to eternal forces, whereby junction is protected from being damaged in the joining processing. Thus, the optical switch can be highly reliable.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: December 12, 2006
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Aoki, Yasuo Yamagishi
  • Patent number: 7139176
    Abstract: A circuit substrate including a silicon substrate with through-holes formed therein, conducting films formed on the inside walls of the through-holes, and an organic resin film formed on the surface of at least one side of the silicon substrate and covering at least parts of the through-holes. Accordingly, even in a case where the through-holes formed, micronized at a small pitch, the substrate does not lower the mechanical strength. Thus, a circuit substrate which is applicable to high-density packaging can be provided.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: November 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
  • Publication number: 20060255817
    Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Application
    Filed: July 14, 2006
    Publication date: November 16, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Yasuo Yamagishi
  • Patent number: 7102367
    Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Yasuo Yamagishi, Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7099534
    Abstract: An optical waveguide and a first lens are formed on an underlying surface. The optical waveguide guides light along a first direction. The first lens is continuous with one end of the waveguide and converges light radiated from the end plane of the optical waveguide and diverging along directions parallel to the underlying surface. A second lens converges light transmitted through the first lens and diverging along directions perpendicular to the underlying surface. A support member supports the first and second lenses. It is possible to prevent a shift of positions of the optical waveguide and lens to be caused by a temperature change and to prevent a light coupling efficiency from being lowered.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Masayuki Kato, Akio Sugama, Koji Tsukamoto, Yasuo Yamagishi
  • Patent number: 7097366
    Abstract: An optoelectronic component is mounted at a precise position on a waveguide substrate so as to reduce loss in propagating light, and electrically connect electrodes on the waveguide substrate and the optoelectronic component. The waveguide substrate has an optical waveguide and a recessed portion for mounting the optoelectronic component, and electrodes are arranged on the recessed portion. A great number of globular elastic conductive particles are distributed on the bottom surface of the recessed portion. Thereafter, the optoelectronic component is placed in the recessed portion so as to press the globular elastic conductive particles, and alignment between the optical waveguide in the waveguide substrate and an optical waveguide in the optoelectronic component is adjusted. Then, the optoelectronic component is fixed to the waveguide substrate with an optical adhesive while the alignment is precisely adjusted.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Aoki, Masayuki Kato, Yasuo Yamagishi, Tomoyuki Akahoshi, Nawalage Florence Cooray, Mamoru Kurashina
  • Patent number: 7043098
    Abstract: The optical device comprises a first substrate 10 having a control circuit formed on; optical waveguide layer 40 formed above the first substrate and having a refractive index changed by electro-optic effect; and second substrates 14a, 14b having prism electrodes 18 for applying voltages to the optical waveguide layer. The control circuit and the prism electrodes are electrically connected to each other via columnar conductors 20. Even in a case where thermal expansion coefficients of the control substrate and of the light deflection substrates are very different from each other, the pins are flexed corresponding to eternal forces, whereby junction is protected from being damaged in the joining processing. Thus, the optical switch can be highly reliable.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: May 9, 2006
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Aoki, Yasuo Yamagishi
  • Patent number: 7025906
    Abstract: A conductive composition layer, conductive particles as a raw material, a conductive composition therefor, a manufacturing method of the conductive composition layer, etc. are provided wherewith heat conductance can be accelerated between electronic devices or electronic devices can be electrically connected. The conductive composition layer is formed by subjecting to heat treatment at a temperature lower than 230° C. a conductive composition comprising conductive particles having a metal base material and a metal coating material thereon as well as a thermosetting resin having a curing temperature that is lower than 230° C. and/or a thermoplastic resin having a melting point that is lower than 230° C.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: April 11, 2006
    Assignee: Fujitsu Limited
    Inventors: Kozo Shimizu, Yasuo Yamagishi
  • Publication number: 20060051895
    Abstract: A method for manufacturing an electronic component-mounted board (X) includes a temperature raising step for heating an electronic component (30A), with a solder bump electrode (31) containing a solder material, to a first temperature higher than the melting point of the solder material, while also heating a wiring board (X?), with an electrode section (21) corresponding to the solder bump electrode (31), to a second temperature lower than the first temperature. The method further includes a joining step for joining the solder bump electrode (31) and the electrode section (21) by pressing the electronic component (30A) against the wiring board (X?), with the solder bump electrodes (31) and the electrode sections (21) abutting against each other.
    Type: Application
    Filed: September 23, 2005
    Publication date: March 9, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Abe, Yasuo Yamagishi