Abstract: In a semiconductor device capable of obtaining an optimum delay time, a plurality of delay circuits are connected in series to one another through points of connections between two adjacent ones of the delay circuits to produce a plurality of reference delay signals derived from the delay circuits. One of the reference delay signals is decided as the optimum delay time with reference to a practical condition. Thus, the delay time can be varied in the semiconductor device.

Abstract: The semiconductor device for setting a delay time, according to the present invention, comprises: a plurality of serially connected delay circuits into which a reference signal is input; a selector switch for selecting one of delay signals output from connection points between the delay circuits; and an internal selection signal generator for producing a selection signal for switching the selector switch to select one of the connection points.

Abstract: A semiconductor integrated circuit device is expected to output a multi-bit output signal at an extremely narrow timing in response to a system clock, wherein the semiconductor integrated circuit device includes synchronous latch circuits, a first phase-locked loop responsive to the system clock for producing a dummy data signal and a high-frequency intermediate clock signal, a delay circuit for producing a delayed clock signal delayed from the system clock by a predetermined number of clock pulses of the high-frequency intermediate clock signal and a second phase-locked loop comparing a dummy output signal with the delayed clock signal for producing a synchronous clock signal at appropriate timing, and the synchronous latch circuits is responsive to the synchronous clock signal for latching data signals and the dummy data signal, thereby outputting the output signals and the dummy output signal within the narrow timing.