Patents by Inventor Yasuomi Tanaka
Yasuomi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210137711Abstract: Provided is a stent that can sufficiently support the inner wall of an in vivo lumen from the inside, and that can be easily collected outside the body after the stent completed its role. The stent 1 is delivered from the dissected base of a patient's leg through the inside of a catheter 2 that is a hollow flexible tube. The stent 1 is a coil (support) member that supports the inner wall of an in vivo lumen from the inside while being placed at a treated area in the in vivo lumen. The stent 1 takes an elongate form to elongate along the inside of the catheter 2 by pulling the stent 1 in a longitudinal direction and a coil form to support the inner wall of an in vivo lumen from the inside by releasing the stent 1. The stent 1 also has a hook 1b for collection at its one end.Type: ApplicationFiled: March 14, 2019Publication date: May 13, 2021Inventors: Yoshihiro FUKUMOTO, Yasuomi TANAKA, Masahiro UMEDA, Kwangwoo NAM
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Publication number: 20210045902Abstract: Provided is a device for collection that can easily collect an object such as a stent from a lumen defined by a lumen wall. The device for collection includes an operation wire that is inserted movably forward and backward inside a catheter that is a hollow flexible tube and a snare wire provided at the tip of the operation wire. The snare wire is formed of one wire, which includes a first loop at the base end side, a second loop at the leading end side, and an intersection of the first loop with the second loop. The snare wire is double looped, in which the first loop and the second loop are approximately concentrically located adjacent to each other. The intersection is located at leading end side of the first loop. The operation wire, the first loop, and the second loop are located on an approximately same plain face.Type: ApplicationFiled: March 13, 2019Publication date: February 18, 2021Inventors: Yoshihiro FUKUMOTO, Kwangwoo NAM, Yasuomi TANAKA, Masahiro UMEDA
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Patent number: 8059834Abstract: A controller 100 updates data LVLm indicative of a level section of an input audio signal and controls a reference level Vr based on a signal CMP representative of a comparison result between the input audio signal and the reference level Vr, and further, controls gains of electronic volumes 10L and 10R in such a manner that these gains become such gains corresponding to the level section of the input audio signal. In this case, the level sections of the input audio signals are related to the gains in such a manner that levels of output signals of the electronic volumes do not exceed a previously set output amplitude upper limit level.Type: GrantFiled: July 6, 2007Date of Patent: November 15, 2011Assignee: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Patent number: 7990211Abstract: A pulse monitor circuit detects the presence or non-presence of the output pulses output from an output stage circuit. The pulse monitor circuit outputs an up signal to the up/down counter when the output pulses do not exist at all and outputs a down signal to the up/down counter when the output pulses exist. The up/down counter outputs a signal for increasing the delay amount of a delay amount variable circuit when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit.Type: GrantFiled: July 11, 2008Date of Patent: August 2, 2011Assignee: Yamaha CorporationInventors: Hirotaka Kawai, Nobuaki Tsuji, Yasuomi Tanaka
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Patent number: 7924089Abstract: A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.Type: GrantFiled: August 30, 2010Date of Patent: April 12, 2011Assignee: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Patent number: 7912112Abstract: A spectrum spreading circuit, includes a control portion that repeats a sequence in which the control portion generates a designation signal for designating all of plural frequencies in prescribed order by selecting a next frequency from the frequencies which have not been selected, and a signal generating portion that sequentially generates output signals having the designated frequencies respectively on the basis of the designation signal.Type: GrantFiled: July 6, 2007Date of Patent: March 22, 2011Assignee: Yamaha CorporationInventors: Hirotaka Kawai, Nobuaki Tsuji, Yasuomi Tanaka
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Publication number: 20110006843Abstract: A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.Type: ApplicationFiled: August 30, 2010Publication date: January 13, 2011Applicant: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Patent number: 7830182Abstract: A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.Type: GrantFiled: September 19, 2008Date of Patent: November 9, 2010Assignee: Yamaha CorporationInventors: Masaya Suzuki, Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Patent number: 7816992Abstract: An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.Type: GrantFiled: July 6, 2007Date of Patent: October 19, 2010Assignee: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Publication number: 20090102516Abstract: A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.Type: ApplicationFiled: September 19, 2008Publication date: April 23, 2009Applicant: Yamaha CorporationInventors: Masaya Suzuki, Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Publication number: 20090027121Abstract: A pulse monitor circuit detects the presence or non-presence of the output pulses output from an output stage circuit. The pulse monitor circuit outputs an up signal to the up/down counter when the output pulses do not exist at all and outputs a down signal to the up/down counter when the output pulses exist. The up/down counter outputs a signal for increasing the delay amount of a delay amount variable circuit when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit.Type: ApplicationFiled: July 11, 2008Publication date: January 29, 2009Applicant: Yamaha CorporationInventors: Hirotaka Kawai, Nobuaki Tsuji, Yasuomi Tanaka
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Publication number: 20080032640Abstract: A spectrum spreading circuit, includes a control portion that repeats a sequence in which the control portion generates a designation signal for designating all of plural frequencies in prescribed order by selecting a next frequency from the frequencies which have not been selected, and a signal generating portion that sequentially generates output signals having the designated frequencies respectively on the basis of the designation signal.Type: ApplicationFiled: July 6, 2007Publication date: February 7, 2008Applicant: Yamaha CorporationInventors: Hirotaka Kawai, Nobuaki Tsuji, Yasuomi Tanaka
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Publication number: 20080018393Abstract: An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.Type: ApplicationFiled: July 6, 2007Publication date: January 24, 2008Applicant: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Publication number: 20080008336Abstract: A controller 100 updates data LVLm indicative of a level section of an input audio signal and controls a reference level Vr based on a signal CMP representative of a comparison result between the input audio signal and the reference level Vr, and further, controls gains of electronic volumes 10L and 10R in such a manner that these gains become such gains corresponding to the level section of the input audio signal. In this case, the level sections of the input audio signals are related to the gains in such a manner that levels of output signals of the electronic volumes do not exceed a previously set output amplitude upper limit level.Type: ApplicationFiled: July 6, 2007Publication date: January 10, 2008Applicant: Yamaha CorporationInventors: Yasuomi Tanaka, Nobuaki Tsuji, Hirotaka Kawai
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Patent number: 6937091Abstract: A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP?). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP?), to a driving circuit (304). As a result, the driving circuits (304, 305) complementarily drive power-MOS transistors (401, 402).Type: GrantFiled: August 1, 2003Date of Patent: August 30, 2005Assignee: Yamaha CorporationInventors: Yasuomi Tanaka, Masao Noro
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Patent number: 6859096Abstract: A detecting circuit (REFH, CM11, LA1, TN1, RN1) which detects an overcurrent flowing through a power-MOS transistor (401) in an output stage to output a first signal (ITN1) is disposed in a first driving circuit (303H) on the side of a high-side driver. Another detecting circuit (REFL, CM21, LA2, TN2, RN2) which detects an overcurrent flowing through a power-MOS transistor (402) in the output stage to output a second signal (ITN2) is disposed in a driving circuit (303L) on the side of a low-side driver. The first signal (ITN1) is converted to a third signal (ITT2) based on a negative power supply (VPP?), by a signal converting circuit. The third signal is added to the second signal. In response to the addition signal, a pulse signal to be input to the driving circuits (303H and 303L) is blocked.Type: GrantFiled: July 30, 2003Date of Patent: February 22, 2005Assignee: Yamaha CorporationInventors: Yasuomi Tanaka, Masao Noro
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Publication number: 20040061552Abstract: A detecting circuit (REFH, CM11, LA1, TN1, RN1) which detects an overcurrent flowing through a power-MOS transistor (401) in an output stage to output a first signal (ITN1) is disposed in a first driving circuit (303H) on the side of a high-side driver. Another detecting circuit (REFL, CM21, LA2, TN2, RN2) which detects an overcurrent flowing through a power-MOS transistor (402) in the output-stage to output a second signal (ITN2) is disposed in a driving circuit (303L) on the side of a low-side driver. The first signal (ITN1) is converted to a third signal (ITT2) based on a negative power supply (VPP−), by a signal converting circuit. The third signal is added to the second signal. In response to the addition signal, a pulse signal to be input to the driving circuits (303H and 303L) is blocked.Type: ApplicationFiled: July 30, 2003Publication date: April 1, 2004Applicant: Yamaha CorporationInventors: Yasuomi Tanaka, Masao Noro
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Publication number: 20040021512Abstract: A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305).complementarily drive power-MOS transistors (401, 402).Type: ApplicationFiled: August 1, 2003Publication date: February 5, 2004Applicant: Yamaha CorporationInventors: Yasuomi Tanaka, Masao Noro
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Patent number: 6317365Abstract: A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level.Type: GrantFiled: June 15, 1999Date of Patent: November 13, 2001Assignee: Yamaha CorporationInventor: Yasuomi Tanaka
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Patent number: 6307788Abstract: A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level.Type: GrantFiled: November 22, 2000Date of Patent: October 23, 2001Assignee: Yamaha CorporationInventor: Yasuomi Tanaka