Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×Mf+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

Abstract: A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.

Abstract: In the present invention, a logic circuit is provided therein with a current supply control circuit for controlling the amount of current supplied to a differential circuit. This current supply control circuit comprises a bypass path for bypassing the current around the differential circuit, a switching transistor interposed in the bypass path for opening/closing the bypass path in accordance with the signal level of a clock signal applied thereto from the outside, and a current amount control transistor for controlling the amount of current supplied to the differential circuit. The current amount control transistor adjusts the amount of current in accordance with the signal level of the clock signal.

Abstract: A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.

Abstract: In the present invention, a logic circuit is provided therein with a current supply control circuit for controlling the amount of current supplied to a differential circuit. This current supply control circuit comprises a bypass path for bypassing the current around the differential circuit, a switching transistor interposed in the bypass path for opening/closing the bypass path in accordance with the signal level of a clock signal applied thereto from the outside, and a current amount control transistor for controlling the amount of current supplied to the differential circuit. The current amount control transistor adjusts the amount of current in accordance with the signal level of the clock signal.

Abstract: This preamplification circuit comprises a first circuit section, second circuit section the input signal of which is the output signal of the first circuit section, and third circuit section which is connected with the input section of the first circuit section and consumes a part of the current to be inputted to a connection point with the input section of the first circuit section and has the capacitance value of the third circuit section set at a value for suppressing a gain peaking of gain frequency characteristics which occurs in the preamplification circuit.

Abstract: Master circuit 1 and slave circuit 2 are designed so that the transistors constituting data-hold differential pairs are smaller in size than the transistors constituting data reading differential pairs. Further, the flip-flop circuit is adapted to operate in an operating speed range in which the currents through the data-hold differential pairs are lower than the currents through the data reading differential pairs, and the currents through the data-hold differential pairs are equal to or lower than the permissible current level of the transistors that constitute the data-hold differential pairs.

Abstract: This preamplification circuit comprises a first circuit section, second circuit section the input signal of which is the output signal of the first circuit section, and third circuit section which is connected with the input section of the first circuit section and consumes a part of the current to be inputted to a connection point with the input section of the first circuit section and has the capacitance value of the third circuit section set at a value for suppressing a gain peaking of gain frequency characteristics which occurs in the preamplification circuit.

Abstract: A semiconductor integrated circuit including interconnect for connecting a current switch circuit and an emitter follower circuit and a method for producing the semiconductor integrated circuit. A matching between a characteristic impedance of the interconnect and an output impedance of the current switch circuit at its output and also an input impedance of the emitter follower circuit at its input in a predetermined frequency range is conducted to prevent an occurrence of distortion of a waveform of a data signal and a gain peaking of frequency characteristic. An impedance converter circuit can be placed at the input or output of the interconnect to match the characteristic impedance of the interconnect.

Abstract: A semiconductor integrated circuit including interconnect for connecting a current switch circuit and an emitter follower circuit and a method for producing the semiconductor integrated circuit. A matching between a characteristic impedance of the interconnect and an output impedance of the current switch circuit at its output and also an input impedance of the emitter follower circuit at its input in a predetermined frequency range is conducted to prevent an occurrence of distortion of a waveform of a data signal and a gain peaking of frequency characteristic. An impedance converter circuit can be placed at the input or output of the interconnect to match the characteristic impedance of the interconnect.

Abstract: An obstacle is opposed to a lower electrode of a metal-insulator-metal capacitor so as to form a gap therebetween, thereafter, insulating material is deposited so as to fill the gap and form a dielectric layer of the metal-insulator-metal capacitor; even if the deposition does not achieve a conformal step coverage, the insulating material in the gap surely isolates the lower electrode from the upper electrode, and the lower electrode is never short-circuited with the upper electrode.