Patents by Inventor Yasushi Deguchi

Yasushi Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7332780
    Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: February 19, 2008
    Assignee: Japan Aerospace Exploration Agency
    Inventors: Sumio Matsuda, Satoshi Kuboyama, Yasushi Deguchi
  • Publication number: 20040007743
    Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.
    Type: Application
    Filed: March 4, 2003
    Publication date: January 15, 2004
    Inventors: Sumio Matsuda, Satoshi Kuboyama, Yasushi Deguchi