Patents by Inventor Yasushi DODA

Yasushi DODA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847524
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Mitsuteru Mushiga, Yasushi Doda
  • Publication number: 20200312859
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Yoshitaka Otsu, Mitsuteru Mushiga, Yasushi Doda
  • Patent number: 9812461
    Abstract: A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel. Source contact via structures are located at each center of a subset of the hexagons that forms a one-dimensional array that extends along the second horizontal direction, each source contact via structure being electrically shorted to a respective source region over, or within, the substrate.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: November 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasushi Doda, Ryoichi Honma
  • Publication number: 20160276360
    Abstract: A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel. Source contact via structures are located at each center of a subset of the hexagons that forms a one-dimensional array that extends along the second horizontal direction, each source contact via structure being electrically shorted to a respective source region over, or within, the substrate.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Inventors: Yasushi DODA, Ryoichi HONMA