Patents by Inventor Yasushi Fukai

Yasushi Fukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497790
    Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second conductivity type separated from each other and provided in an upper layer portion of the semiconductor portion, a gate electrode provided on the semiconductor portion, a first contact piercing the gate electrode, a second contact piercing the gate electrode, a first insulating film provided between the first semiconductor layer and a side surface of the first contact and between the first contact and the gate electrode, and a second insulating film provided between the second semiconductor layer and a side surface of the second contact and between the second contact and the gate electrode. A lower portion of the first contact is disposed inside the first semiconductor layer, a lower end of the first contact is connected to the first semiconductor layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 3, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masahito Nishigoori, Hiroyoshi Kitahara, Yasushi Fukai, Naozumi Terada
  • Publication number: 20190088753
    Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, a first semiconductor layer and a second semiconductor layer of a second conductivity type separated from each other and provided in an upper layer portion of the semiconductor portion, a gate electrode provided on the semiconductor portion, a first contact piercing the gate electrode, a second contact piercing the gate electrode, a first insulating film provided between the first semiconductor layer and a side surface of the first contact and between the first contact and the gate electrode, and a second insulating film provided between the second semiconductor layer and a side surface of the second contact and between the second contact and the gate electrode. A lower portion of the first contact is disposed inside the first semiconductor layer, a lower end of the first contact is connected to the first semiconductor layer.
    Type: Application
    Filed: March 14, 2018
    Publication date: March 21, 2019
    Inventors: Masahito Nishigoori, Hiroyoshi Kitahara, Yasushi Fukai, Naozumi Terada
  • Publication number: 20150263163
    Abstract: A semiconductor device includes first and second semiconductor layers, first and second semiconductor regions, a source region, a drain region, and a gate electrode. The second semiconductor layer of a first conductive type is formed over the first semiconductor layer. The first semiconductor region of a second conductive type is formed on a surface of the second semiconductor layer. The source region of the first type is formed on a surface of the first semiconductor region. The drain region of the first type is formed on a surface of the first semiconductor layer having the first type, is separated from the source region. The second semiconductor region of the second type is provided between the drain region and the first semiconductor layer. The gate electrode is formed over the second semiconductor layer and is provided between the drain region and the source region.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Rieko AKIMOTO, Yasushi FUKAI
  • Publication number: 20120139005
    Abstract: According to one embodiment, a semiconductor device includes a p-type semiconductor layer, an n-type source region, an insulator, an n-type semiconductor region, an n-type drain region, a p-type channel region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and an electrode. The source region is provided on a surface of the p-type semiconductor layer. The insulator is provided in a trench formed extending in a thickness direction of the p-type semiconductor layer from the surface of the p-type semiconductor layer. The n-type semiconductor region is provided on the surface of the p-type semiconductor layer between the source region and the insulator. The drain region is provided on the surface of the p-type semiconductor layer between the source region and the n-type semiconductor region and separated from the source region and the n-type semiconductor region.
    Type: Application
    Filed: March 21, 2011
    Publication date: June 7, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takehito IKIMURA, Rieko Akimoto, Kiminori Watanabe, Koji Shirai, Yasushi Fukai