Yasushi Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A hand-written character/graphic is recognized in a character recognition mode or a graphic recognition mode designated in accordance with stroke information supplied from a tablet input device which samples the hand-written character/graphic and converts it to the stroke information. The recognition mode is automatically designated by comparing a longer one of projection lengths on x-axis and y-axis of stroke coordinates with a predetermined threshold for a hand-written character input.
Abstract: An input-output coordinate transforming method for an input-integerated display apparatus of a structure in which an input coordinate designating part is integrally combined with a screen of a display device, wherein coordinates inputted through the input coordinate designating part by an operator are subjected to coordinate transformation before being supplied to the display device so as to make an input point on the input coordinate designating means coincide with an output point on the display screen when observed by the operator.
Abstract: An apparatus for recognizing and displaying handwritten characters and figures in which input stroke information on a handwritten input character or figure is read out by an electromagnetic tablet, recognition means performs character/figure recognition on the basis of the feature of the input stroke information, display means displays the input stroke information and the result of recognition, and when the result of recognition is displayed on a display screen of the display means, stroke information having been used for recognition is erased from the display screen, and stroke information which is not yet used for recognition, is left on the display screen.
Abstract: A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
Abstract: There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.
Abstract: In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.
Abstract: A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.
Abstract: A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
Abstract: In a data processing system having an instruction pipeline in which each instruction is allotted for execution, part by part, to segments provided in the instruction pipeline so that the first segment executes a part of one instruction allotted thereto, while the successive segments execute respective parts of the preceding instructions allotted thereto, a control of the instruction pipeline is arranged to provide the segments with individual reference clock signals whose timings are determined separately depending on the capacity of each segment for execution of the allotted part of each instruction and also variable depending on the actual condition of the system in execution of each instruction.
Abstract: An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.